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general description the MAX1816/max1994 are dual step-down controllers for notebook computer applications. buck1 is a cpu core regulator with dynamically adjustable output, ultra- fast transient response, high dc accuracy, and high effi- ciency. buck2 is an adjustable step-down regulator for i/o and memory supplies. both regulators employ maxim? proprietary quick-pwm control architecture. this fast- response, constant-on-time pwm control scheme handles wide input/output voltage ratios with ease and provides 100ns ?nstant?on-response to load transients, while main- taining a relatively constant switching frequency. the MAX1816/max1994 also have a linear-regulator controller for low-voltage auxiliary power supplies. the cpu regulator supports ?ctive voltage positioning to reduce output bulk capacitance and lower power dis- sipation. a programmable gain amplifier allows the use of lower value sense resistors. four fixed-gain settings are available (0, 1.5, 2, and 4). a differential remote- sense amplifier is also included to more accurately con- trol the voltage at the load. accuracy is further enhanced with an internal integrator. the MAX1816/max1994 include a specialized digital interface that makes them suitable for mobile cpu and video processor applications. the power-good (pgood) output for the core regulator is forced high during vid transitions, and the lingood output for the linear regulator includes a 1ms (min) turn-on delay. buck1, buck2, and the linear regulator feature overvolt- age protection (ovp). the detection threshold for buck1 is adjusted with an external resistive voltage-divider, while the ovp thresholds for buck2 and the linear regulator are fixed. connecting the ovpset pin to v cc disables ovp for buck1 and buck2, but not the linear regulator. the MAX1816 features an output-voltage adjustment range from 0.6v to 1.75v. similarly, the max1994 is adjustable from 0.925v to 2.0v, using an alternate vid code set. while in suspend mode, the adjustment range is 0.7v to 1.075v for both the MAX1816 and max1994. both parts are available in 48-pin thin qfn packages. applications mobile cpu core and video processors memory i/o and vid supplies 3- to 4-cell li+ battery to cpu core supply small notebook computers features dual quick-pwm architecture ?% v out accuracy 5-bit on-board d/a converter +0.60v to +1.75v output adjust range (MAX1816) +0.70v to +2.00v output adjust range (max1994) voltage-positioning gain and offset control +2v to +28v battery input range differential remote sense (buck1) linear-regulator controller 200/300/550/1000khz switching frequency 2.2ma (typ) i cc supply current 20? (max) shutdown supply current independent power-good outputs (pgood, lingood) MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ________________________________________________________________ maxim integrated products 1 19-2569; rev 0; 10/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin-package MAX1816 etm -40 c to +100 c 48 thin qfn max1994 etm -40 c to +100 c 48 thin qfn ilim2 cs2 fb2 ref linbse lingood linfb ovpset time v cc agnd out2 cs1+ cs1- fbs gds gain ofs0 ofs1 dpslp ofs2 sus cc ilim1 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 d4 s0 s1 skp2/sdn ton pgood lin/sdn d3 d2 d1 d0 lx1 dh1 perf dl1 pgnd v dd dl2 dh2 lx2 v+ bst2 bst1 thin qfn 7mm 7mm MAX1816 max1994 skp1/sdn top view 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 pin configuration quick-pwm is a trademark of maxim integrated products, inc.
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to agnd............................................................-0.3v to +30v v cc , v dd to agnd...................................................-0.3v to +6v pgnd, gds to agnd ......................................................... 0.3v skp1/ sdn , skp2/ sdn , lin/ sdn to agnd............-0.3v to +16v linbse, sus, perf, dpslp , pgood, lingood, cs1+, cs1-, fbs, d0 d4, out2 to agnd.....................................................-0.3v to +6v ofs0, ofs1, ofs2, ilim1, ilim2, fb2, ref, ton, time, ovpset, s0, s1, gain, cc, linfb to agnd ....................-0.3v to (v cc + 0.3v) dl1, dl2 to pgnd .....................................-0.3v to (v dd + 0.3v) dh1 to lx1 ..............................................-0.3v to (v bst1 + 0.3v) dh2 to lx2 ..............................................-0.3v to (v bst2 + 0.3v) bst1 to lx1..............................................................-0.3v to +6v bst2 to lx2..............................................................-0.3v to +6v lx1, lx2, cs2 to agnd ............................................-2v to +30v ref short circuit to agnd.........................................continuous linbse short circuit to +6v.......................................continuous continuous power dissipation (t a = +70 c) 48-pin thin qfn (derate 26.3mw/ c above +70 c) .2105mw operating temperature range .........................-40 c to +100 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (circuit of figure 1, v+ = 15v, v out1 = 1.20v, v out2 = 2.50v, v cc = v dd = 5.0v, v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5.0v, t a = 0? to +85? . typical values are at t a = +25 c, unless otherwise noted.) parameter conditions min typ max units ton = ref, open, or v cc 228 battery voltage v+ ton = gnd 2 16 input voltage range v cc , v dd 4.5 5.5 v dac codes from 0.600v to 1.750v (MAX1816) buck1 dc output voltage accuracy v+ = 4.5v to 28v, includes load regulation errors, ofs_ = gds = agnd, cs1+ = cs1- = fbs dac codes from 0.700v to 2.000v (max1994) -1 +1 % fb2 = gnd 2.475 2.500 2.525 fb2 = v cc 1.782 1.800 1.818 buck2 error comparator threshold (dc output voltage accuracy) (note 1) v+ = 4.5v to 28v fb2 = out2 0.990 1.000 1.010 v out2 adjust range 1.0 5.5 v fb2 gnd level voltage level to enable internal feedback for buck2 with v out2 = 2.5v 0.05 v fb2 external feedback level voltage level to enable external feedback for buck2 with fb2 regulated to 1.0v nominal 0.15 1.90 v fb2 v cc level voltage level to enable internal feedback for buck2 with v out2 = 1.8v 2.10 v gain = gnd 0 gain = ref 1.425 1.500 1.575 gain = open 1.900 2.000 2.100 voltage-positioning gain gain = v cc 3.800 4.000 4.200 v/v
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v out1 = 1.20v, v out2 = 2.50v, v cc = v dd = 5.0v, v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5.0v, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) parameter conditions min typ max units current-sense differential input range (cs1+, cs1-) 200 mv remote-sense differential input range (cs1+, fbs) 300 mv remote-sense differential input range (gds, agnd) 200 mv cs1+, fbs input bias current -300mv < v cs1+ - v fbs < +300mv -60 +60 a cs1- input bias current -100mv < v cs1+ - v cs1- < +100mv, v cs1- = v fbs -60 +60 a gds input bias current -3 +3 a fb2 input bias current -0.2 +0.2 a out2 input resistance 70 k ? 252khz nominal, r time = 143k ? -8 +8 time frequency accuracy 53khz nominal to 530khz nominal, r time = 680k ? to 68k ? -12 +12 % v+ = 5v, cs1- = 1.2v ton = gnd (1000khz) 230 260 290 ton = ref (550khz) 165 190 215 ton = open (300khz) 320 355 390 buck1 on-time (note 2) v+ = 12v, cs1- = 1.2v ton = v cc (200khz) 465 515 565 ns v+ = 5v, out2 = 2.5v ton = gnd (715khz) 630 720 810 ton = ref (390khz) 495 550 605 ton = open (390khz) 495 550 605 buck2 on-time (note 2) v+ = 12v, out2 = 2.5v ton = v cc (260khz) 740 825 910 ns ton = open, ton = v cc (note 2) 425 500 minimum off-time ton = gnd, ton = ref (note 2) 325 375 ns quiescent supply current (v cc ) measured at v cc , with fbs, out2, fb2, and linfb forced above the no-load regulation point 2200 3800 a partial shutdown supply current (linear regulator on only) v skp1/ sdn = 0v, v skp2/ sdn = 0v, v lin/ sdn = 5v; measured at v cc , with fbs and linfb forced above the no-load regulation point 425 650 a partial shutdown supply current (buck1 and linear regulator) v skp1/ sdn = 5v, v skp2/ sdn = 0v, v lin/ sdn = 5v; measured at v cc , with fbs and linfb forced above the no-load regulation point 1825 3000 a partial shutdown supply current (buck2 only) v skp1/ sdn = 0v, v skp2/ sdn = 5v, v lin/ sdn = 0v; measured at v cc , with out2 and fb2 forced above the regulation point 600 1100 a quiescent supply current (v dd ) measured at v dd , with fbs, out2, and fb2 forced above the no-load regulation point <1 5 a
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v out1 = 1.20v, v out2 = 2.50v, v cc = v dd = 5.0v, v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5.0v, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) parameter conditions min typ max units quiescent battery current measured at v+ 25 40 a shutdown supply current (v cc ) v skp1/ sdn = 0v, v skp2/ sdn = 0v, and v lin/ sdn = 0v 4 10 a shutdown supply current (v dd ) v skp1/ sdn = 0v, v skp2/ sdn = 0v, and v lin/ sdn = 0v <1 5 a shutdown battery current v skp1/ sdn = v skp2/ sdn = 0v, measured at v+, with v cc = v dd = 0v or 5v <1 5 a reference voltage v cc = 4.5v to 5.5v, i ref = 50a sourcing 1.98 2.00 2.02 v i ref = 0 to 50a 0 7 reference load regulation i ref = 50a to 100a 0 7 mv reference sink current ref in regulation 10 a ovpset disable mode threshold voltage at ovpset above which the ovp functions are disabled for buck1 and buck2 v cc - 1.5 v cc - 0.5 v ovpset default mode threshold for buck1 voltage at ovpset below which the ovp thresholds are set to their default values 0.4 0.6 v MAX1816 1.95 2.00 2.05 overvoltage trip threshold for buck1 (fixed ovp threshold) ovpset = gnd, measured at fbs max1994 2.20 2.25 2.30 v MAX1816 0.95 1.00 1.05 v ovpset = 1.0v, measured at fbs max1994 1.075 1.125 1.175 MAX1816 1.95 2.00 2.05 overvoltage trip threshold for buck1 (adjustable threshold) v ovpset = 2.0v, measured at fbs max1994 2.20 2.25 2.30 v overvoltage trip threshold for buck2 measured at out2 (or fb2 if external feedback is used) 113 115 117 % ovpset bias current 0v < v ovpset < v cc -100 +100 na overvoltage fault propagation delay fbs, out2, fb2, and linfb forced 2% above the no-load trip threshold 10 s output undervoltage protection threshold with respect to unloaded output voltage, fbs, and out2 (fb2 in external feedback) 65 70 75 % output undervoltage fault propagation delay fbs, out2, fb2, and linfb forced 2% below trip threshold 10 s output undervoltage protection blanking time for fbs from skp1/ sdn signal going high; clock speed set by r time (note 3) 256 clks output undervoltage protection blanking time for out2 from skp2/ shdn signal going high; clock speed set by r time (note 3) 4096 clks linear regulator (linfb) undervoltage protection blanking time linear regulator; from lin/ sdn signal going high; clock speed set by r time (note 3) 512 clks
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v out1 = 1.20v, v out2 = 2.50v, v cc = v dd = 5.0v, v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5.0v, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) parameter conditions min typ max units ilim1 default threshold v cc - 1.5 v cc - 1.0 v cc - 0.5 v buck1 current-limit threshold (fixed) cs1+ - cs1-; v ilim1 = v cc 40 50 60 mv cs1+ - cs1-; v ilim1 = 0.5v 40 50 60 buck1 current-limit threshold (adjustable) cs1+ - cs1-; v ilim1 = 2.0v 160 200 240 mv buck1 negative current-limit threshold (fixed) cs1+ - cs1-; v ilim1 = v cc -90 -72 -55 mv ilim1 input bias current 0 to 2v -100 +100 na cs2 input bias current 0 to 28v -1 +1 a ilim2 default threshold v cc - 1.5 v cc - 1.0 v cc - 0.5 v buck2 current-limit threshold (fixed) agnd - cs2; v ilim2 = v cc 40 50 60 mv agnd - cs2; v ilim2 = 0.5v 40 50 60 buck2 current-limit threshold (adjustable) agnd - cs2; v ilim2 = 2.0v 160 200 240 mv buck2 negative current-limit threshold (fixed) agnd - cs2; v ilim2 = v cc -90 -72 -55 mv ilim2 input bias current 0 to 2v -100 +100 na thermal-shutdown threshold 15 c hysteresis 160 o c v cc undervoltage lockout threshold rising edge, hysteresis = 20mv 4.10 4.45 v dh1 gate-driver on-resistance bst1 lx1 forced to 5v (note 4) 1 4.5 ? dl1 high state (pullup) (note 4) 1 4.5 dl1 gate-driver on-resistance dl1 low state (pulldown) (note 4) 0.35 2 ? dh1 gate-driver source/sink current dh1 forced to 2.5v, bst lx forced to 5v 1.5 a dl1 gate-driver sink current dl1 forced to 2.5v 5 a dl1 gate-driver source current dl1 forced to 2.5v 1.5 a dl1 rising 35 dead time dh1 rising 26 ns dh2 gate-driver on-resistance bst2 lx2 forced to 5v (note 4) 2 8 ? dl2 high state (pullup) (note 4) 2 8 dl2 gate-driver on-resistance dl2 low state (pulldown) (note 4) 0.7 3 ?
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 6 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v out1 = 1.20v, v out2 = 2.50v, v cc = v dd = 5.0v, v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5.0v, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) parameter conditions min typ max units d h 2 g ate- d r i ver s our ce/s i nk c ur r ent dh2 forced to 2.5v, bst2 lx2 forced to 5v 0.75 a dl2 gate-driver sink current dl2 forced to 2.5v 2.5 a dl2 gate-driver source current dl2 forced to 2.5v 0.75 a dl2 rising 35 dead time dh2 rising 26 ns linfb input bias current v linfb = 1.035v -100 +100 na v linfb = 1.05v, v linbse = 5v 0.4 linbse drive current v linfb = 0.965v, v linbse = 0.5v 20 ma linfb regulation voltage v linbse = 5v, i linbse = 4ma (sink) 0.988 1.000 1.017 v linfb load regulation v linbse = 5v, i linbse = 2ma to 10ma (sink) -2.2 -1.2 % logic input high voltage d0 d4, sus, perf, lin/ sdn 2.4 v logic input low voltage d0 d4, sus, perf, lin/ sdn 0.8 v logic input high voltage dpslp 0.8 v logic input low voltage dpslp 0.4 v logic input current d0 d4, sus, perf, lin/ sdn , dpslp = 0v or 5v -1 +1 a four-level logic v cc level ton, s0, s1, gain logic input high level v cc - 0.4 v four-level logic float level ton, s0, s1, gain logic input upper midlevel 3.15 3.85 v four-level logic ref level ton, s0, s1. gain logic input lower midlevel 1.65 2.35 v four-level logic gnd level ton, s0, s1, gain logic input low level 0.5 v skp1/ sdn , skp2/ sdn , s0, s1, gain, and ton logic-input current skp1/ sdn , skp2/ sdn , ton, s0, s1, gain forced to gnd or v cc -3 +3 a skp1/ sdn , skp2/ sdn skip level skp1/ sdn , skp2/ sdn logic input high level 2.8 v skp1/ sdn , skp2/ sdn pwm level skp1/ sdn , skp2/ sdn logic input float level 1.4 2.2 v skp1/ sdn , skp2/ sdn shutdown level skp1/ sdn , skp2/ sdn logic input low level 0.4 v skp1/ sdn test mode input voltage range to enable no-fault mode, 4.5v < v cc < 5.5v 10.8 13.2 v pgood lower trip threshold measured at fbs, out2, and fb2 with respect to unloaded output voltage, falling edge, typical hysteresis = 1% -12.0 -10.0 -8.0 % lingood lower trip threshold and linfb undervoltage protection threshold measured at linfb with respect to unloaded output voltage, falling edge (note 5) -12.0 -10.0 -8.0 % pgood upper trip threshold measured at fbs, out_, fb2 with respect to unloaded output voltage, rising edge, typical hysteresis = 1% 8.0 10.0 12.0 %
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers _______________________________________________________________________________________ 7 electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v out1 = 1.20v, v out2 = 2.50v, v cc = v dd = 5.0v, v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5.0v, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) parameter conditions min typ max units lingood upper trip threshold and linfb overvoltage trip threshold measured at linfb with respect to unloaded output voltage, rising edge (note 5) 8.0 10.0 12.0 % pgood propagation delay out_, fb2 forced 2% above or below pgood trip threshold 10 s lingood turn-on delay linfb forced 2% above lingood lower trip threshold 1 ms lingood turn-off delay linfb forced 2% below lingood lower trip threshold 10 s pgood transition delay after the output-voltage transition on buck1 is complete (pgood blanking is enabled for n + 4 clocks, blanking is excluded in startup and shutdown) 4 clk forced-pwm mode transition delay after the output-voltage transition on buck1 is complete (forced-pwm mode persists for n + 32 clocks for all transitions) 32 clk open-drain output low voltage (pgood, lingood) i sink = 3ma 0.4 v open-drain leakage current (pgood, lingood) high state, forced to 5.5v 1 a input current ofs0 ofs2 -0.1 +0.1 a ofs positive offset when programmed to zero deviation in the output voltage when tested with ofs_ connected to ref 2 mv ? v out / ? v ofs, ? v ofs = (0.8v - 0v) 0.119 0.125 0.131 ofs gain ? v out / ? v ofs , ? v ofs = (2.0v - 1.2v) 0.119 0.125 0.131 v/v
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 8 _______________________________________________________________________________________ electrical characteristics (circuit of figure 1, v+ = 15v, v out1 = 1.20v, v out2 = 2.50v, v cc = v dd = 5.0v, v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5.0v, t a = -40 c to +100 c , unless otherwise noted.) (note 6) parameter conditions min typ max units ton = ref, open, or v cc 228 battery voltage v+ ton = gnd 2 16 input voltage range v cc , v dd 4.5 5.5 v dac codes from 0.600v to 1.750v (MAX1816) buck1 dc output-voltage accuracy v+ = 4.5v to 28v, includes load regulation errors, ofs_ = gds = agnd, cs1+ = cs1- = fbs dac codes from 0.700v to 2.000v (max1994) -1.5 +1.5 % fb2 = gnd 2.463 2.538 fb2 = v cc 1.773 1.827 buck2 error comparator threshold (dc output-voltage accuracy) (note 1) v+ = 4.5v to 28v fb2 = out2 0.985 1.015 v out2 adjust range 1.0 5.5 v gain = ref 1.425 1.575 gain = open 1.900 2.100 voltage-positioning gain gain = v cc 3.800 4.200 v/v current-sense differential input range (cs1+, cs1-) 200 mv remote-sense differential input range (cs1+, fbs) 300 mv remote-sense differential input range (gds, agnd) 200 mv cs1+, fbs input bias current -300mv < v cs1+ - v fbs < +300mv -60 +60 a cs1- input bias current -100mv < v cs1+ - v cs1- < +100mv, v cs1- = v fbs -60 +60 a 252khz nominal; r time =143k ? -8 +8 time frequency accuracy 53khz nominal to 530khz nominal; r time = 680k ? to 68k ? -12 +12 % v+ = 5v, cs1- = 1.2v ton = gnd (1000khz) 230 290 ton = ref (550khz) 165 215 ton = open (300khz) 320 390 buck1 on-time (note 2) v+ = 12v, cs1- = 1.2v ton = v cc (200khz) 465 565 ns v+ = 5v, out2 = 2.5v ton = gnd (715khz) 630 810 ton = ref (390khz) 495 605 ton = open (390khz) 495 605 buck2 on-time (note 2) v+ = 12v, out2 = 2.5v ton = v cc (260khz) 740 910 ns ton = open, ton = v cc (note 2) 500 minimum off-time ton = gnd, ton = ref (note 2) 375 ns quiescent supply current (v cc ) measured at v cc , with fbs, out2, fb2, and linfb forced above the no-load regulation point 4500 a
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers _______________________________________________________________________________________ 9 electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v out1 = 1.20v, v out2 = 2.50v, v cc = v dd = 5.0v, v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5.0v, t a = -40 c to +100 c , unless otherwise noted.) (note 6) parameter conditions min typ max units partial shutdown supply current (linear regulator on only) v skp1/ sdn = 0v, v skp2/ sdn = 0v, v lin/ sdn = 5v; measured at v cc , with fbs and linfb forced above the no-load regulation point 750 a partial shutdown supply current (buck1 and linear regulator) v skp1/ sdn = 5v, v skp2/ sdn = 0v, v lin/ sdn = 5v; measured at v cc , with fbs and linfb forced above the no-load regulation point 3400 a partial shutdown supply current (buck2 only) v skp1/ sdn = 0v, v skp2/ sdn = 5v, v lin/ sdn = 0v; measured at v cc , with out2 and fb2 forced above the regulation point 1400 a quiescent supply current (v dd ) measured at v dd , with fbs, out2, and fb2 forced above the no-load regulation point, t a = -40 c to +85 c 5 a quiescent battery current measured at v+ 40 a shutdown supply current (v cc ) v skp1/ sdn = 0v, v skp2/ sdn = 0v, and v lin/ sdn = 0v, t a = -40 c to +85 c 10 a shutdown supply current (v dd ) v skp1/ sdn = 0v, v skp2/ sdn = 0v, and v lin/ sdn = 0v, t a = -40 c to +85 c 5 a shutdown battery current v skp1/ sdn = v skp2/ sdn = 0v, measured at v+, with v cc = v dd = 0v or 5v, t a = -40 c to +85 c 5 a reference voltage v cc = 4.5v to 5.5v, i ref = 50a sourcing 1.98 2.02 v i ref = 0 to 50a 0 7 reference load regulation i ref = 50a to 100a 0 7 mv reference sink current ref in regulation 10 a ovpset disable mode threshold voltage at ovpset above which the ovp functions are disabled for buck1 and buck2 v cc - 1.5 v cc - 0.5 v ovpset default mode threshold for buck1 voltage at ovpset below which the ovp thresholds are set to their default values 0.4 0.6 v MAX1816 1.95 2.05 overvoltage trip threshold for buck1 (fixed ovp threshold) ovpset = gnd, measured at fbs max1994 2.20 2.30 v MAX1816 0.95 1.05 v ovpset = 1.0v, measured at fbs max1994 1.075 1.175 MAX1816 1.95 2.05 overvoltage trip threshold for buck1 (adjustable threshold) v ovpset = 2.0v, measured at fbs max1994 2.20 2.30 v overvoltage trip threshold for buck2 measured at out2 (or fb2 if external feedback is used) 113 117 % output undervoltage protection threshold with respect to unloaded output voltage fbs and out2 (fb2 in external feedback) 65 75 %
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 10 ______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v out1 = 1.20v, v out2 = 2.50v, v cc = v dd = 5.0v, v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5.0v, t a = -40 c to +100 c , unless otherwise noted.) (note 6) parameter conditions min typ max units ilim1 default threshold v cc - 1.5 v cc - 0.5 v buck1 current-limit threshold (fixed) cs1+ - cs1-; v ilim1 = v cc 40 60 mv cs1+ - cs1-; v ilim1 = 0.5v 40 60 buck1 current-limit threshold (adjustable) cs1+ - cs1-; v ilim1 = 2.0v 160 240 mv buck1 negative current-limit threshold (fixed) cs1+ - cs1-; v ilim1 = v cc -90 -55 mv ilim2 default threshold v cc - 1.5 v cc - 0.5 v buck2 current-limit threshold (fixed) agnd - cs2; v ilim2 = v cc 40 60 mv agnd - cs2; v ilim2 = 0.5v 40 60 buck2 current-limit threshold (adjustable) agnd - cs2; v ilim2 = 2.0v 160 240 mv buck2 negative current-limit threshold (fixed) agnd - cs2; v ilim2 = v cc -90 -55 mv v cc undervoltage lockout threshold rising edge, hysteresis = 20mv 4.10 4.45 v dh1 gate-driver on-resistance bst1 lx1 forced to 5v (note 4) 4.5 ? dl1 high state (pullup) (note 4) 4.5 dl1 gate-driver on-resistance dl1 low state (pulldown) (note 4) 2 ? dh2 gate-driver on-resistance bst2 lx1 forced to 5v (note 4) 8 ? dl2 high state (pullup) (note 4) 8 dl2 gate-driver on-resistance dl2 low state (pulldown) (note 4) 3 ? v linfb = 1.05v, v linbse = 5v 0.4 linbse drive current v linfb = 0.965v, v linbse = 0.5v 20 ma linfb regulation voltage v linbse = 5v, i linbse = 4ma (sink) 0.988 1.017 v linfb load regulation v linbse = 5v, i linbse = 2ma to 10ma (sink) -2.2 % logic input high voltage d0 d4, sus, perf, lin/ sdn 2.4 v logic input low voltage d0 d4, sus, perf, lin/ sdn 0.8 v logic input high voltage dpslp 0.8 v logic input low voltage dpslp 0.4 v four-level logic v cc level ton, s0, s1, gain logic input high level v cc - 0.4 v four-level logic float level ton, s0, s1, gain logic input upper midlevel 3.15 3.85 v four-level logic ref level ton, s0, s1, gain logic input lower midlevel 1.65 2.35 v four-level logic gnd level ton, s0, s1, gain logic input low level 0.5 v
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 11 electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v out1 = 1.20v, v out2 = 2.50v, v cc = v dd = 5.0v, v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5.0v, t a = -40 c to +100 c , unless otherwise noted.) (note 6) parameter conditions min typ max units skp1/ sdn , skp2/ sdn skip level skp1/ sdn , skp2/ sdn logic input high level 2.8 v skp1/ sdn , skp2/ sdn pwm level skp1/ sdn , skp2/ sdn logic input float level 1.4 2.2 v skp1/ sdn , skp2/ sdn shutdown level skp1/ sdn , skp2/ sdn logic input low level 0.4 v pgood lower trip threshold m easur ed at fbs , ou t2, and fb2 w i th r esp ect to unl oad ed outp ut vol tag e, fal l i ng ed g e, typ i cal hyster esi s = 1% -12.5 -7.5 % lingood lower trip threshold and linfb undervoltage protection threshold measured at linfb with respect to unloaded output voltage, falling edge (note 5) -12.5 -7.5 % pgood upper trip threshold measured at fbs, out_, fb2 with respect to unloaded output voltage, rising edge, typical hysteresis = 1% 7.5 12.5 % lingood upper trip threshold and linfb overvoltage trip threshold measured at linfb with respect to unloaded output voltage, rising edge (note 5) 7.5 12.5 % lingood turn-on delay linfb forced 2% above lingood lower trip threshold 1 ms open-drain output low voltage (pgood, lingood) i sink = 3ma 0.4 v ofs positive offset when programmed to zero deviation in the output voltage when tested with ofs_ connected to ref 2 mv ? v out / ? v ofs , ? v ofs = (0.8v - 0v) 0.119 0.131 ofs gain ? v out / ? v ofs , ? v ofs = (2.0v - 1.2v) 0.119 0.131 v/v note 1: dc output accuracy specifications for buck2 refer to the trip level of the error amp. the output voltage has a dc regulation higher than the trip level by 50% of the ripple. in skip mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load. note 2: on-time and minimum off-time specifications for both buck1 and buck2 are measured from 50% to 50% at the dh_ pin with lx_ forced to zero, bst_ forced to 5v, and a 500pf capacitor from dh_ to lx_ to simulate external mosfet gate capacitance. actual in-circuit times can be different due to mosfet switching speeds. note 3: this does not include the time for ref to start up if required. note 4: production testing limitations due to package handling require relaxed maximum on-resistance specifications for the thin qfn package. note 5: the lingood signal is latched low under a fault condition of linfb dropping below 90% or rising above 110% of the nomi- nal set point. the lingood signal does not go high again until the fault latch is reset. note 6: specifications from -40 c to +100 c are guaranteed by design, not production tested.
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 12 ______________________________________________________________________________________ figure 1. standard application circuit 0 ? agnd float lingood pgood d1: cmsh5-40 d2: ec31qs03l d3, d4: cmpsh-3 pgnd dac inputs suspend inputs control inputs float (gain = 2) ilim2 r5 100 ? r2 0.005 ? 1% 3.3v bias supply r6 10 ? r3 280k ? 1% r4 49.9k ? 1% r1 0.001 ? 1% r19 2 ? r20 2 ? r17 196k ? 1% r11 100k ? r8 20k ? 1 % r9 100k ? 1 % r7 220 ? r12 100k ? r10 143k ? ref q5 fzt749 v lin 1.20v c5 1000pf c8 4.7 f c9 10 f c6 0.22 f c7 1 f c3 0.1 f c2 0.1 f c10 22nf c1 2.2 f c11 0.047 f c12 0.047 f c4 47pf cs2 fb2 ref linbse lingood linfb ovpset time v cc agnd out2 cs1+ cs1- fbs gds gain ofs0 ofs1 dpslp ofs2 sus cc ilim1 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 d4 s0 s1 skp2/sdn ton pgood lin/sdn d3 d2 d1 d0 lx1 dh1 perf dl1 pgnd v dd dl2 dh2 lx2 v+ bst2 bst1 MAX1816 max1994 skp1/sdn 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 r15 196k ? 1% r13 196k ? 1% r18 4.99k ? 1% r16 3.48k ? 1% r14 2k ? 1% q4 d2 c out2 330 f c in2 10 f v out2 2.5v c in1 3 10 f c out1 3 330 f c remote v out1 0.6v to 1.75v (MAX1816) 0.7v to 2.0v (max1994) pc board trace resistance input voltage 7v to 24v pc board trace resistance l2 1.2 h q3 q1 q2 d3 d4 d1 l1 0.6 h v dd , 5v bias supply ref v dd
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 13 figure 2. high-current master-slave application circuit agnd (master) agnd (slave) float pgood pgnd dac inputs suspend inputs control inputs float (gain = 2) ilim2 r5 100 ? r2 0.005 ? 1% 3.3v bias supply r6 10 ? 0 ? 0 ? r3 280k ? 1% r4 49.9k ? 1% r1 0.001 ? 1% r19 2 ? r20 2 ? r17 196k ? 1% r8 .20k ? 1% r9 100k ? 1% r7 220 ? r12 100k ? r10 143k ? ref q5 v lin 1.2v fzt749 c5 1000pf c8 4.7 f c9 10 f c6 0.22 f c7 1 f c3 0.1 f c2 0.1 f c10 22nf c19 100pf c1 2.2 f c4 47pf cs2 fb2 ref linbse lingood linfb ovpset time v cc agnd out2 cs1+ cs1- fbs gds gain ofs0 ofs1 dpslp ofs2 sus cc ref ilim1 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 d4 s0 s1 skp2/sdn ton pgood lin/sdn d3 d2 d1 d0 lx1 dh1 perf dl1 pgnd v dd dl2 dh2 lx2 v+ bst2 bst1 MAX1816 max1994 skp1/sdn 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 r15 196k ? 1% r13 196k ? 1% r18 4.99k ? 1% r16 3.48k ? 1% r14 2k ? 1% r28 2 ? r26 20 ? r27 2 ? r23 49.9k ? 1% r22 280k ? 1% r21 34.8k ? q4 d2 c out2 2 270 f c in2 10 f c in3 3 10 f v out2 2.5v c in1 3 10 f c out1 6 330 f c remote v out1 0.6v to 1.75v (MAX1816) 0.7v to 2.0v (max1994) pc board trace resistance input voltage 7v to 24v pc board trace resistance l2 1.2 h q3 q1 q2 q6 q7 d3 d4 d5 d1 l1 0.6 h v dd , 5v bias supply c12 0.1 f c13 1 f c16 22nf c15 270pf c14 0.22 f ref v dd ref r24 0.001 ? 1% l3 0.6 h d6 c17 0.047 f c18 0.047 f lx cm+ cm- ton float cs- cs+ dh v cc v dd dd dl pgnd gnd pol comp trig ilim limit v+ bst max1980 d1, d6: cmsh5-40 d2: ec31qs03l d3, d4, d5: cmpsh-3
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 14 ______________________________________________________________________________________ efficiency vs. load current (buck1 v out1 = 1.25v) MAX1816 toc01 load current (a) efficiency (%) 10 1 0.1 60 70 80 90 100 50 0.01 100 skip mode v in = 20v forced pwm v in = 7v v in = 12v output voltage vs. load current (buck1) MAX1816 toc02 load current (a) output voltage (v) 25 20 15 10 5 1.21 1.22 1.23 1.24 1.25 1.26 1.20 030 skip mode forced pwm efficiency vs. load current (buck2 v out2 = 2.5v) MAX1816 toc03 load current (a) efficiency (%) 1 0.1 60 70 80 90 100 50 0.01 10 skip mode forced pwm v in = 20v v in = 7v v in = 12v typical operating characteristics (circuit of figure 1, v+ = 12v, v dd = v cc = v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5v; v in(ldo) = 3.3v, v out(buck1) = 1.25v, v out(buck2) = 2.5v; t a = +25 c, unless otherwise noted.) output voltage vs. load current (buck2) MAX1816 toc04 load current (a) output voltage (v) 8 2 6 4 2.52 2.54 2.56 2.58 2.50 010 skip mode forced pwm frequency vs. load current (buck1 and buck2) MAX1816 toc05 load current (a) frequency (khz) 15 10 5 100 200 300 400 0 020 buck2 pwm mode buck2 skip mode buck1 pwm mode buck1 skip mode frequency vs. input voltage (buck1 and buck2) MAX1816 toc06 input voltage (v) frequency (khz) 20 15 10 300 350 400 250 525 buck2 i out2 = 8a buck2 i out2 = 1a buck1 i out1 = 20a buck1 i out1 = 3a frequency vs. temperature (buck1 and buck2) MAX1816 toc07 temperature ( c) frequency (khz) 80 60 40 20 0 -20 300 350 400 450 250 -40 100 buck2 i out2 = 8a buck1 i out1 = 20a output current at current limit vs. temperature MAX1816 toc08 temperature ( c) output current at current limit (a) 80 60 40 20 0 -20 10 20 30 40 0 -40 100 buck1 buck2 no-load supply current vs. input voltage (skip mode) MAX1816 toc09 input voltage (v) supply current ( a) 20 15 10 300 600 900 1200 1500 1800 2100 2400 2700 3000 0 525 i+ i cc + i dd
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 15 no-load supply current vs. input voltage (pwm mode) MAX1816 toc10 input voltage (v) supply current (ma) 20 15 10 10 20 30 40 50 0 525 i+ i cc + i dd buck1 load transient response (skip mode) MAX1816 toc11 20 s/div b a c 1.25v 20a 20a a: load current, 20a/div b: output voltage, 100mv/div, ac-coupled c: inductor current, 20a/div 1.15v 0 0 1.35v buck1 load transient response (pwm mode) MAX1816 toc12 20 s/div b a c 1.25v 20a 20a a: load current, 20a/div b: output voltage, 100mv/div, ac-coupled c: inductor current, 20a/div 1.15v 0 0 1.35v buck2 load transient response (skip mode) MAX1816 toc13 20 s/div b a 2.6v 5a a: output voltage, 100mv/div, ac-coupled b: inductor current, 5a/div 10a 2.5v 0 2.4v typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v dd = v cc = v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5v; v in(ldo) = 3.3v, v out(buck1) = 1.25v, v out(buck2) = 2.5v; t a = +25 c, unless otherwise noted.)
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 16 ______________________________________________________________________________________ buck2 load transient response (pwm mode) MAX1816 toc14 20 s/div b a 2.6v 5a a: output voltage, 100mv/div, ac-coupled b: inductor current, 5a/div 10a 2.5v 0 2.4v buck1 startup waveform (pwm mode, no load) MAX1816 toc15 100 s/div b a c 10a 2v 2v a: output voltage, 1v/div b: inductor current, 10a/div c: skp1/sdn signal, 2v/div 0 1v 0 0 buck1 startup waveform (pwm mode, i out1 = 20a) MAX1816 toc16 100 s/div b a c 10a 2v 2v a: output voltage, 1v/div b: inductor current, 10a/div c: skp1/sdn signal, 2v/div 0 1v 0 0 20a buck2 startup waveform (pwm mode, no load) MAX1816 toc17 40 s/div b a c 10a 4v 2v a: output voltage, 2v/div b: inductor current, 10a/div c: skp2/sdn signal, 2v/div 0 2v 0 0 typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v dd = v cc = v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5v; v in(ldo) = 3.3v, v out(buck1) = 1.25v, v out(buck2) = 2.5v; t a = +25 c, unless otherwise noted.)
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 17 buck2 startup waveform (pwm mode, i out2 = 8a) MAX1816 toc18 40 s/div b a c 10a 4v 2v a: output voltage, 2v/div b: inductor current, 10a/div c: skp2/sdn signal, 2v/div 0 2v 0 0 buck1 dynamic output-voltage transition (pwm mode) MAX1816 toc19 100 s/div b a c 0 10a 5v v out1 = 1.40v to 1.00v to 1.40v i out1 = 3a, r time = 143k ? a: output voltage, 500mv/div b: inductor current, 10a/div c: pgood signal, 5v/div d: vid bit, 5v/div 5v 1.5v 0 1v 0 d buck1 dynamic output-voltage transition (skip mode) MAX1816 toc20 100 s/div b a c 0 10a 5v v out1 = 1.40v to 1.00v to 1.40v i out1 = 1a, r time = 143k ? a: output voltage, 500mv/div b: inductor current, 10a/div c: pgood signal, 5v/div d: vid bit, 5v/div 5v 1.5v 0 1v 0 d buck1 dynamic output-voltage transition (skip mode) MAX1816 toc21 100 s/div b a c 0 10a 5v v out1 = 1.00v to 0.60v to 1.00v i out1 = 1a, r time = 143k ? a: output voltage, 500mv/div b: inductor current, 10a/div c: pgood signal, 5v/div d: sus signal, 5v/div 5v 1v 0 0.5v 0 d typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v dd = v cc = v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5v; v in(ldo) = 3.3v, v out(buck1) = 1.25v, v out(buck2) = 2.5v; t a = +25 c, unless otherwise noted.)
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 18 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v dd = v cc = v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5v; v in(ldo) = 3.3v, v out(buck1) = 1.25v, v out(buck2) = 2.5v; t a = +25 c, unless otherwise noted.) buck1 shutdown waveform (skip mode, no load) MAX1816 toc22 100 s/div b a c 10a 2v 5v a: output voltage, 1v/div b: inductor current, 10a/div c: skp1/sdn signal, 5v/div 0 1v 0 0 -10a buck1 shutdown waveform (pwm mode, i out2 = 20a) MAX1816 toc23 100 s/div b a c 10a 2v 5v a: output voltage, 1v/div b: inductor current, 10a/div c: skp1/sdn signal, 5v/div 0 1v 0 0 20a output offset vs. ofs input voltage MAX1816 toc24 v ofs (v) output offset (mv) 1.5 0.5 1.0 -100 0 100 200 -200 0 2.0 undefined region buck1 output-voltage distribution (v out1 = 1.25v, sample size = 55) MAX1816 toc25 buck1 output voltage (v) sample percentage (%) 1.250 10 20 30 0 1.248 1.252 1.249 1.251
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 19 reference voltage distribution (v ref = 2.0v, sample size = 55) MAX1816 toc26 reference voltage (v) sample percentage (%) 2.000 10 20 30 0 2.002 1.999 2.001 linear regulator load regulation MAX1816 toc27 load current (ma) output voltage (v) 100 10 1 1.202 1.204 1.206 1.208 1.210 1.200 0.1 1000 linear regulator line regulation MAX1816 toc28 input voltage (v) output voltage (v) 10 8 6 4 2 1.17 1.18 1.19 1.20 1.21 1.22 1.16 012 linear regulator load transient response MAX1816 toc29 20 s/div b a 1.2v a: load current, 200ma/div b: output voltage, 10mv/div, ac-coupled 400ma 1.19v 200ma 0 linear regulator startup waveform MAX1816 toc30 20 s/div b a c 2v 200ma a: v lin/sdn , 5v/div b: v lin = 1.2v, 1v/div c: i lin = 300ma, 200ma/div 0 5v 0 0 400ma 1v typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v dd = v cc = v skp1/ sdn = v skp2/ sdn = v lin/ sdn = 5v; v in(ldo) = 3.3v, v out(buck1) = 1.25v, v out(buck2) = 2.5v; t a = +25 c, unless otherwise noted.)
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 20 ______________________________________________________________________________________ pin name function 1 ilim1 buck1 current-limit adjustment. the cs1+ - cs1- current-limit threshold defaults to 50mv if ilim1 is connected to v cc . in adjustable mode, the current-limit threshold voltage is precisely 1/10th of the voltage at ilim1. the logic threshold for switchover to the default value is approximately v cc - 1v. 2 cc integrator time constant control input. this pin allows the integrator to be compensated independent of the voltage-positioning sense feedback path. connect a 47pf to 1000pf capacitor from this pin to ground to control the integration time constant. 3 cs1+ positive voltage-positioning and current-sense input for buck1. the current-limit sense voltage for cs1+ - cs1- is 1/10th of the voltage at the ilim1 input. the cs1+ and cs1- inputs are also used for active voltage positioning, with the voltage-positioning gain set with the gain pin. connecting the gain pin to ground disables voltage positioning. positive and negative current limits are always active. 4 cs1- negative voltage-positioning and current-sense input for buck1. cs1- is also the output sense input for calculating ton. the current-limit sense voltage for cs1+ - cs1- is 1/10th of the voltage at the ilim1 input. the cs1+ and cs1- inputs are also used for active voltage positioning, with the voltage-positioning gain set with the gain pin. connecting the gain pin to ground disables voltage positioning. positive and negative current limits are always active. 5 fbs output feedback remote-sense input for buck1. connect fbs directly to the load. fbs internally connects to an amplifier that fine-tunes the output voltage, compensating for voltage drops from the regulator output to the load. 6 gds ground remote-sense input for buck1. connect gds directly to the load. gds internally connects to an amplifier that fine-tunes the output voltage, compensating for voltage drops from the regulator ground to the load ground. 7 gain voltage-positioning gain control. gain is a four-level logic input that selects the voltage-positioning gain (see cs1+, cs1- pins). the gain setting does not affect current-limit functions. connecting gain to gnd disables the voltage positioning by setting the gain to zero. connecting gain to ref sets the gain to 1.5. leaving gain open sets the gain to 2. connecting gain to v cc sets the gain to 4. gnd = 0; ref = 1.5; open = 2; v cc = 4. 8 ofs0 voltage-divider input for voltage-positioning offset control. ofs0 ofs2 are selected based on the sus, perf, and dpslp signals. for 0v < ofs_ < 0.8v, 0.125 times the voltage at ofs_ is subtracted from the output. for 1.2v < ofs_ < 2.0v, 0.125 times the difference between ref and ofs_ is added to the output. voltages in the range of 0.8v < ofs_ < 1.2v are not permitted (see table 7). 9 ofs1 voltage-divider input for voltage-positioning offset control. ofs0 ofs2 are selected based on the sus, perf, and dpslp signals. for 0v < ofs_ < 0.8v, 0.125 times the voltage at ofs_ is subtracted from the output. for 1.2v < ofs_ < 2.0v, 0.125 times the difference between ref and ofs_ is added to the output. voltages in the range of 0.8v < ofs_ < 1.2v are not permitted (see table 7). 10 ofs2 voltage-divider input for voltage-positioning offset control. ofs0 ofs2 are selected based on the sus, perf, and dpslp signals. for 0v < ofs_ < 0.8v, 0.125 times the voltage at ofs_ is subtracted from the output. for 1.2v < ofs_ < 2.0v, 0.125 times the difference between ref and ofs_ is added to the output. voltages in the range of 0.8v < ofs_ < 1.2v are not permitted (see table 7). 11 sus suspend mode control input. the sus signal causes the s0 and s1 inputs to take precedence over the vid code setting and ofs inputs. when sus is high, the state of the s0 and s1 inputs are decoded to select the appropriate dac code and the offset is forced to zero (see the dac inputs and internal multiplexer section). 12 dpslp deep sleep control input. this logic control input goes to the offset selection multiplexer that determines which, if any, offset control inputs are read (ofs0 ofs2). this input is compatible with 1.5v logic (see table 7). 13 d0 vid code input. d0 is the least significant bit (lsb). pin description
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 21 pin name function 14 d1 vid code input 15 d2 vid code input 16 d3 vid code input 17 d4 vid code input. d4 is the most significant bit (msb). 18 s0 suspend mode voltage-select input. s0 and s1 are four-level logic inputs that select the suspend mode vid code for the suspend mode multiplexer inputs. if sus is high, the suspend mode vid code is delivered to the dac overriding any other voltage setting (see the dac inputs and internal multiplexer section). 19 s1 suspend mode voltage-select input. s0 and s1 are four-level logic inputs that select the suspend mode vid code for the suspend mode multiplexer inputs. if sus is high, the suspend mode vid code is delivered to the dac overriding any other voltage setting (see the dac inputs and internal multiplexer section). 20 skp1/ sdn combined shutdown and skip-mode control input for buck1. always start buck2 before starting buck1. connect skp1/ sdn to v cc or drive the pin above 2.8v with external 3.3v-powered cmos logic for normal pfm/pwm operation. connect skp1/ sdn to gnd or drive the pin below 0.5v to shut down buck1. in shutdown mode, dl1 is forced to v dd in order to enforce overvoltage protection when the regulator is powered down. leave skp1/ sdn floating for the low-noise forced pwm operation. low-noise forced-pwm mode causes the inductor current to reverse at light loads and suppresses pulse-skipping operation. skp1/ sdn can also be used to disable both over- and undervoltage protection circuits and clear the fault latch. this test mode is enabled by forcing the pin to 10.8v < v skp1/ sdn < 13.2v. while in the test mode, the regulator performs the normal pfm/pwm operation. skp1/ sdn cannot withstand the battery voltage. 21 skp2/ sdn combined shutdown and skip-mode control input for buck2. always start buck2 before starting buck1. connect skp2/ sdn to v cc or drive the pin above 2.8v with external 3.3v-powered cmos logic for normal pfm/pwm operation. connect skp2/ sdn to gnd or drive the pin below 0.5v to shut down buck2. in shutdown mode, dl2 is forced to v dd if the overvoltage protection is enabled. this is done in order to enforce overvoltage protection even when the regulator is powered down. leave skp2/ sdn floating for the low-noise forced pwm operation. low-noise forced-pwm mode causes the inductor current to recirculate at light loads and suppresses pulse-skipping operation. if ovpset = v cc , then dl2 is forced low in shutdown mode. skp2/ sdn cannot withstand the battery voltage. 22 lin/ sdn linear regulator shutdown control input. connect lin/ sdn to v cc or drive the pin above 2.4v to turn on the linear regulator. connect lin/ sdn to gnd or drive the pin below 0.8v to shut down the linear regulator. in shutdown mode, linbse is forced to a high-impedance state preventing sufficient drive to the external pnp power transistor in the regulator. lin/ sdn cannot withstand the battery voltage. 23 pgood open-drain power-good output. pgood is forced low during power-up and power-down transitions on buck1. in normal operation, if fbs and out2 (fb2) are in regulation, then pgood is high. pgood is forced low when skp1/ sdn is low. if skp2/ sdn is low, out2 (fb2) does not affect pgood. normally, pgood is forced high for all vid transitions, and stays high for 4 time clock periods after the d/a count is equalized. if out2 is enabled during these conditions and a fault occurs on buck2, then pgood goes low. a pullup resistor on pgood causes additional finite shutdown current. 24 ton on-time selection control input. this four-level input sets the k factor that determines the dh on-time. the ton times for buck2 are shifted to minimize beating between the two regulators. gnd = 1000khz (buck1) and 715khz (buck2), ref = 550khz (buck1) and 390khz (buck2), open = 300khz (buck1) and 390khz (buck2), v cc = 200khz (buck1) and 260khz (buck2). pin description (continued)
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 22 ______________________________________________________________________________________ pin name function 25 ovpset overvoltage protection control input. this pin controls the ovp functions for buck1 and buck2. linfb is not affected by ovpset. connect ovpset to v cc to disable overvoltage protection for both buck1 and buck2. connect ovpset to gnd for default overvoltage threshold of 2.0v (MAX1816) or 2.25v (max1994) for buck1, measured at fbs. the ovp threshold for buck2 is always at 115% of the nominal output voltage. the ovp threshold for buck1 can be adjusted by connecting ovpset between 1.0v and 2.0v. an overvoltage condition occurs if v fbs > v ovpset (MAX1816) or v fbs > 1.125 v ovpset (max1994). undervoltage protection thresholds are always enabled and are not affected by this pin. 26 time slew rate adjustment input. connect a resistor from time to gnd to set the internal slew-rate clock. a 680k ? to 68k ? resistor to gnd sets the clock from 53khz to 530khz, f slew = 252khz (143k ? / r time ). 27 linfb linear regulator feedback input. the linear regulator s feedback set point is 1.0v. connect a resistive voltage-divider from the collector of the external pnp pass transistor to linfb. the dc bias current in the voltage-divider should be greater than 10a. the linear regulator is active whenever lin/ sdn is high. 28 lingood open-drain power-good output for the linear regulator. as soon as linfb is in regulation, lingood goes high after a 1ms minimum delay. when the output goes out of regulation or lin/ sdn goes low, lingood is forced low within approximately 10s. a pullup resistor on lingood causes additional shutdown current. 29 linbse linear regulator base drive. connect linbse to the base of an external pnp power transistor. add a 220 ? pullup resistor between the base and the emitter. 30 agnd analog ground. connect the MAX1816/max1994s exposed backside pad and low-current ground terminations to agnd. the current-limit comparator s ground sense for buck2 also connects to agnd. 31 v cc analog supply voltage input for buck1, buck2, and the linear regulator. this pin supplies all power to the device except for the mosfet drivers. the range for v cc is 4.5v to 5.5v. bypass v cc to gnd with a minimum capacitance of 1f. the maximum resistance between v cc and v dd should be 10 ? . 32 ref 2.0v reference output. bypass ref to gnd with a minimum capacitance of 0.22f. the reference is trimmed with a nominal 50a load, and can source a total of 100a for external loads. loading ref greater or less than 50a decreases output-voltage accuracy according to the limits defined in the electrical characteristics table. 33 fb2 adjustable feedback input for buck2. in adjustable mode, fb2 regulates to 1.00v. it also selects default voltage. connect fb2 to gnd for 2.5v output, or connect fb2 to v cc for 1.8v output. 34 out2 output voltage connection for buck2. connect directly to the junction of the output filter capacitors. out2 senses the output voltage to determine the on-time and also serve as the feedback input in fixed-output modes. 35 cs2 current-sense input for buck2. for accurate current limit, connect cs2 to a sense resistor between the source of the low-side mosfet and ground. alternatively, cs2 can be connected to lx2 for lossless current sensing across the low-side mosfet. the current-limit sense voltage for cs2 is set at the ilim2 36 ilim2 buck2 current-limit adjustment input. the current-limit threshold measured between agnd and cs2 defaults to 50mv when ilim2 is connected to v cc . in adjustable mode, the current-limit threshold voltage is precisely 1/10th of the voltage at ilim2. the logic threshold for switchover to the default value is approximately v cc - 1v. 37 v+ battery voltage sense input. v+ is used only for pwm one-shot timing. dh1 and dh2 on-times are inversely proportional to input voltage over a 2v to 28v range. 38 bst2 buck2 boost flying capacitor connection. an optional resistor in series with bst2 allows the dh1 pullup current to be adjusted. pin description (continued)
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 23 detailed description the MAX1816/max1994 are dual step-down controllers for notebook computer applications. the controllers include a cpu regulator (buck1) that features a dynamically adjustable output with offset control and a programmable suspend mode voltage. this regulator is capable of delivering very large currents at the high efficiencies needed for leading-edge cpu core appli- cations. a second step-down regulator (buck2) is included to generate i/o or memory supplies. both reg- ulators employ maxim s proprietary quick-pwm control architecture. a linear-regulator controller is also includ- ed for low-voltage auxiliary power supplies. all of the regulators have independent shutdown control inputs. the linear regulator includes a power-good output that is independent of the combined power-good output for buck1 and buck2. 5v bias supply (v cc and v dd ) the MAX1816/max1994 require an external 5v bias supply in addition to the battery. typically, this 5v bias supply is the notebook computer s 5v system supply. keeping the bias supply external to the ic improves effi- ciency and eliminates the cost associated with the 5v linear regulator that would otherwise be needed to sup- ply the pwm controllers and gate drivers of buck1 and buck2. if stand-alone capability is needed, the 5v sup- ply can be generated with an external linear regulator. the 5v bias supply must provide v cc for the pwm con- troller s internal reference, bias, and logic; and v dd for the gate drivers. the maximum bias supply current is: i bias = i cc + f (q g1 + q g2 + q g3 + q g4 ) = 20ma to 80ma (typ) where i cc is 2.2ma (typ), f is the switching frequency, and q g1 ,q g2 ,q g3 , and q g4 are the total gate charge specifications at v gs = 5v in the mosfet data sheets. v+ and v dd can be connected if the input power source is a fixed 4.5v to 5.5v supply. if the 5v bias supply is powered up prior to the battery supply, the enable signals (skp_/ sdn ) must be delayed until the battery voltage is present to ensure startup. pin name function 39 lx2 buck2 inductor connection. lx2 is the internal lower supply rail for the dh2 high-side gate driver. 40 dh2 buck2 high-side gate-driver output. dh2 swings from lx2 to bst2. 41 dl2 buck2 low-side gate-driver output. dl2 swings from pgnd to v dd . dl2 is forced high when MAX1816/max1994 detect an overvoltage fault. when the regulator powers down, dl2 is forced high if ovp is enabled, and is forced low if ovp is disabled. 42 v dd supply voltage input for dl1 and dl2 gate drivers. connect v dd to the system supply voltage (4.5v to 5.5v). bypass v dd to pgnd with a 2.2f or greater ceramic capacitor. 43 pgnd power ground. ground connection for low-side gate drivers dl1 and dl2. 44 dl1 buck1 low-side gate-driver output. dl1 swings from pgnd to v dd . dl1 is forced high when MAX1816/max1994 detect an overvoltage fault. when the regulator powers down, dl1 is forced high. 45 perf performance mode control input. this logic-control input goes to the offset selection mux that determines which, if any, offset control inputs are read (ofs0 ofs2). this input is compatible with 3.3v logic (see table 7). 46 dh1 buck1 high-side gate-driver output. dh1 swings from lx1 to bst1. 47 lx1 buck1 inductor connection. lx1 is the internal lower supply rail for the dh1 high-side gate driver. 48 bst1 buck1 boost flying capacitor connection. an optional resistor in series with bst1 allows the dh1 pullup current to be adjusted. pin description (continued)
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 24 ______________________________________________________________________________________ table 1. component selection for standard applications component buck1 (circuits of figures 1 and 2) buck2 (circuits of figures 1 and 2) slave (circuit of figure 2) input voltage range 7v to 24v 7v to 24v 7v to 24v output voltage 0.6v to 1.75v (MAX1816), 0.7v to 2.0v (max1994) 2.5v 0.6v to 1.75v (MAX1816), 0.7v to 2.0v (max1994) output current 20a 7a 20a frequency 300khz 300khz 300khz high-side mosfet (2) n-channel international rectifier irf7811w n-channel international rectifier irf7811w (2) n-channel international rectifier irf7811w low-side mosfet (2) n-channel international rectifier irf7822 fairchild fds7764a n-channel international rectifier irf7822 fairchild fds7764a (2) n-channel international rectifier irf7822 fairchild fds7764a input capacitor (3) 10f, 25v x5r ceramic taiyo yuden tmk432bj106km tdk c4532x5r1e106m 10f, 25v x5r ceramic taiyo yuden tmk432bj106km tdk c4532x5r1e106m (3) 10f, 25v x5r ceramic taiyo yuden tmk432bj106km tdk c4532x5r1e106m output capacitor (3) 330f, 2.5v, 10m ? sp panasonic eefue0e331xr (1) 330f, 2.5v, 10m ? sp panasonic eefue0e331xr (3) 330f, 2.5v, 10m ? sp panasonic eefue0e331xr inductor 0.6h panasonic etqp6f0r6bfa toko eh125c-r60n sumida cdep134h-0r6 1.2h toko eh125c-1r2n sumida cdep134h-1r2 panasonic etqp6f1r2bfa 0.6h panasonic etqp6f0r6bfa toko eh125c-r60n sumida cdep134h-0r6 current-sense resistor 1m ? 1%, 1w panasonic erjm1wtj1m0u 5m ? 1%, 1w panasonic erjm1wsf5m0u 1m ? 1%, 1w panasonic erjm1wtj1m0u table 2. component suppliers supplier phone website capacitors panasonic 847-468-5624 www.panasonic.com sanyo 619-661-6835 www.sanyovideo.com taiyo yuden 408-573-4150 www.t-yuden.com tdk 847-803-6100 www. tdk.com inductors panasonic 847-468-5624 www.panasonic.com sumida 408-982-9660 www.sumida.com mosfets fairchild semiconductor 888-522-5372 www.fairchildsemi.com international rectifier 310-322-3331 www.irf.com siliconix 203-268-6261 www.vishay.com
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 25 free-running, constant on-time pwm controller with input feed-forward both buck1 and buck2 employ maxim s proprietary quick-pwm control architecture. the control scheme is a pseudo fixed-frequency, constant-on-time current- mode type with voltage feed forward (figures 3, 4, and 5). it relies on the output ripple voltage to provide the pwm ramp signal. this signal can come from the out- put filter capacitor s esr or a dedicated sense resistor. the control algorithm is simple: the high-side switch on- time is determined solely by a one-shot whose period is inversely proportional to input voltage and directly pro- portional to output voltage. another one-shot sets a minimum off-time (425ns, typ). the on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the current-limit threshold, and the minimum off-time one-shot has timed out. on-time one-shot (ton) the heart of the pwm core is the one-shot that sets the high-side switch on-time (figures 4 and 5). this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltages. the high-side switch on-time is inversely pro- portional to the battery voltage as measured by the v+ input, and proportional to the output voltage. this algo- rithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. the benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455khz if band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output-voltage ripple: on-time = k (v out + 0.075v) / v in where k is set by the ton pin-strap connection and 0.075v is an approximation to accommodate for the expected drop across the low-side mosfet switch (table 3). the on-times for buck1 have nominal frequency set- tings of 200khz, 300khz, 550khz, or 1000khz, while the on-times for buck2 are shifted to minimize beating between the two regulators. the corresponding fre- quency settings for buck2 are 260khz, 390khz, 390khz, and 715khz. the buck2 on-times for ton = open and ton = v cc are shifted down to improve the efficiency. the buck2 on-times for ton = gnd and ton = ref are shifted up to avoid beating, yet maintain the efficiency. the latter settings were not shifted down because the resulting frequencies would be too high. the on-time one-shot has good accuracy at the operat- ing points specified in the electrical characteristics ( 10% at 200khz and 300khz, 12.5% at 550khz and 1000khz for buck1). on-times at operating points far removed from the conditions specified in the electrical characteristics can vary over a wider range. for example, the 1000khz setting typically runs about 10% slower with inputs much greater than 5v due to the very short on-times required. on-times translate only roughly to switching frequencies. the on-times guaranteed in the electrical characteristics are influenced by switching delays in the external high- side mosfets. resistive losses, including the inductor, both mosfets, output capacitor esr, and pc board copper losses tend to raise the switching frequency at higher output currents. also, the dead-time effect increases the effective on-time, reducing the switching frequency. it occurs only in pwm mode (skp_/ sdn = open) and during dynamic output-voltage transitions (buck1) when the inductor current reverses at light or negative load currents. with reversed inductor current, the inductor s emf causes lx to go high earlier than normal, extending the on-time by a period equal to the dh_ low-to-high dead time. table 3. approximate k-factor errors ton buck1 k-factor (s) buck1 frequency (khz) buck1 k-factor error (%) buck2 k-factor (s) buck2 frequency (khz) buck2 k-factor error (%) gnd 1.0 1000 12.5 1.4 715 12.5 open 1.8 550 12.5 2.56 390 10 ref 3.3 300 10 2.56 390 10 v cc 5.0 200 10 3.84 260 10
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 26 ______________________________________________________________________________________ figure 3. functional diagram cs1- ref 5v bias supply v out1 buck2 dh2 v+ dl2 cs2 out2 fb2 ilim2 pgood2 ovpen ton2 ref ton2 pgood1 ovpen ton1 ton1 ref v+ dh1 dl1 cs1+ cs1- fbs gds ilim1 cc dh2 lx2 bst2 dl2 v dd cs2 out2 fb2 ilim2 ref dh1 bst1 lx1 dl1 cs1+ fbs gds ilim1 cc ref mux out bits in bits out vid0?id4 vid mux sus d0?4 four-level decode register s0-s1 sus sus ofs control state machine perf ofs0?fs2 sel i_offset i_offset ovpset fault threshold control ofs_sel offset control input 0 ? pgnd agnd ovpset perf on-time selector ton1 ton2 ton n.c. d0-d4 v+ buck1 5 5 2 suspend inputs dac inputs dac bits dac bits i_offset i_offset v out2 2.5v skp2/sdn skp1/sdn v cc v dd input 7v to 24v lin/sdn lin/sdn 2v ref ref agnd ref pgnd control inputs ovpen skp1/sdn skp2/sdn gain gain ton1 present-state dac bits register vid rom digital comparator ton2 ovpen faultlr linbse lingood p good linfb 3.3v bias supply lingood linear reg 5 5 x x < y x > y x = y rtime time up down osc out clock up/down counter oscillator dac bits out dac bits dac bits y offset control 3 5 5 dpslp dpslp lin/sdn v lin pgood MAX1816 max1994
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 27 for loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switch- ing frequency is: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; v drop2 is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and pc board resistances; and t on is the on-time calculat- ed by the MAX1816/max1994. f vv tvv out drop on in drop = + + 1 2 () figure 4. buck1 pwm control diagram s r q toff one-shot q q trig zero crossing ovp/uvp detector reset out timer on/off control ton one-shot q trig on-time compute gain- state decoder r-2r dac dac amplifier 10k ? error amplifier v+ out1 ton1 ref cc pgood1 skp1/sdn dac bits to dh1 driver input to dl1 driver input ilim1 fbs i_offset cs1+ cs1- gain ref - 10% ref + 10% 10k ? 10k ? /a vps 10k ? /a vps 10k ? 70k ? 8.6r1 0.4r1 r1 fbs gds gnd i_gds s r q gm gm ovpen ovpen
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 28 ______________________________________________________________________________________ buck1 integrator buck1 includes a transconductance integrator (figure 4) that provides a fine adjustment to the output regula- tion point. the integrator forces the dc average of the feedback voltage to equal the vid dac setting. the cir- cuit has the ability to lower the output voltage by 3% and raise it by 3%. the differential input voltage range for the amplifier is at least 60mv total, including dc offset and ac ripple. the integration time constant can be easily set with a capacitor at the cc pin. use a capacitance of 47pf to 1000pf (47pf typ). the transconductance of the ampli- fier is 80s (typ). figure 5. buck2 pwm control diagram s r q toff one-shot q q trig zero crossing ovp/uvp detector reset out timer on/off control ton one-shot q trig on-time compute error amplifier v+ out2 ton2 ref pgood2 skp2/sdn to dh2 driver input to dl2 driver input ilim2 cs2 gnd fb2 out2 fixed 1.5v dual-mode feedback mux fixed 1.8v ref - 10% ref + 10% 1v 2v s r q ovpen ovpen r r
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers buck1 differential remote-sense amplifier (fbs, gds) the MAX1816/max1994 include differential remote- sense inputs to eliminate the effect of voltage drops down the pc board traces and through the processor s power leads. the fbs and gds inputs enable true differ- ential remote sense of the load voltage. the two inputs measure the voltage directly across the load to provide a signal that is summed with the feedback signals that set the voltage-positioned output. connect the feedback sense input (fbs) directly to the positive load terminal and connect the ground sense input (gds) directly to the negative load terminal. modern microprocessors now include dedicated v cc and ground-sense pins to facilitate the measurement of the chip s supply voltage. buck1 voltage-positioning and current-sense inputs (cs1+, cs1-) the cs1+ and cs1- pins are differential inputs that measure the voltage drop across the sense resistor of buck1 for current-limiting, zero-crossing detection and active voltage positioning (figure 4). the current-limit threshold is adjusted with an external resistive voltage- divider at ilim1. a 10a (min) divider current is recom- mended. the current-limit threshold adjustment range is from 25mv to 250mv. in adjustable mode, the cur- rent-limit threshold is precisely 1/10th of the voltage at ilim1. the default current limit is 50mv when ilim1 is connected to v cc . the logic threshold for switchover to the default value is approximately v cc - 1v.the default current limit accommodates the low voltage drop expected across the sense resistor. the current-limit circuit of buck1 employs a unique valley current-sensing algorithm (figure 6). if the magnitude of the current-sense voltage between cs1+ and cs1- is above the current-limit threshold, the pwm is not allowed to initiate a new cycle. the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the sense resistance, induc- tor value, and battery voltage. there is also a negative current limit that prevents excessive reverse inductor currents when v out1 is sinking current in pwm mode. the negative current-limit threshold is set to approxi- mately 140% of the positive current limit and therefore tracks the positive current limit when ilim1 is adjusted. the gain pin controls the voltage-positioning gain. the slope of the output voltage as a function of load current is set by measuring the output current with a sense resistor (r sense ) in series with the inductor. an ampli- fied version of this signal is fed back into the loop to decrease the output voltage. the required offset is added through the ofs0 ofs2 inputs (see the buck1 output-voltage offset control section). the exact rela- tionship for the output of buck1 can be described with the following equation: v out1 = v set - a vps (v cs1+ - v cs1- ) + v os sf where v set is the programmed output voltage (see tables 5 and 6), v os is the offset voltage generated from the selected ofs_ pin, sf is a scale factor (0.125) for the offset voltage, and a vps is the differential volt- age-positioning gain set with the gain pin. since v cs1+ - v cs1- = i load r sense , substituting the differential sense voltage yields: v out1 = v set - a vps i load r sense + v os sf the gain pin is a four-level logic input. when gain is set to gnd, ref, open, and v cc , the differential volt- age gains are 0, 1.5, 2, and 4, respectively. grounding gain disables the voltage-positioning function but does not disable the current limit. buck2 current-sense input (cs2) buck2 uses the voltage at the cs2 pin to estimate the inductor current and determine the zero crossing for controlling pulse-skipping operation (figure 5). connect cs2 to the current-sense resistor (figure 1) for the best possible current-limit accuracy. however, the improved accuracy is achieved at the expense of the additional power loss in the sense resistor. cs2 can be connected to lx2 for lossless current sensing. in this case, the trade-off is that the current limit becomes dependent on the low-side mosfet s r ds(on) with its inherent inaccuracies and thermal drift. inductor current i limit i load 0 time i peak figure 6. valley current-limit threshold point ______________________________________________________________________________________________________ 29
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 30 ______________________________________________________________________________________ like buck1, the current-limit circuit of buck2 also employs valley current sensing (figure 6). if the magni- tude of the current-sense voltage at cs2 is above the current-limit threshold, the pwm is not allowed to initiate a new cycle. the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit character- istic and maximum load capability are a function of the sense resistance, inductor value, and battery voltage. there is also a negative current limit that prevents excessive reverse inductor currents when v out2 is sinking current in pwm mode. the negative current- limit threshold is set to approximately 140% of the posi- tive current limit and therefore tracks the positive current limit when ilim2 is adjusted. the current-limit threshold is adjusted with an external resistive voltage-divider at ilim2. a 10a (min) divider current is recommended. the current-limit threshold adjustment range is from 25mv to 250mv. in adjustable mode, the current-limit threshold voltage is precisely 1/10th of the voltage at ilim2. the threshold defaults to 50mv when ilim2 is connected to v cc . the logic threshold for switchover to the 50mv default value is approximately v cc - 1v. the default current limit accommodates the low voltage drop expected across the sense resistor. carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the cur- rent-sense signal seen by cs2. because cs2 is not a real differential current-sense input, minimize the return impedance from the sense resistor to the power ground to reduce voltage errors when measuring the current. in figure 1, the schottky diode (d2) provides a current path parallel to the q4/r2 current path. accurate cur- rent sensing demands d2 to be off while q4 conducts. avoid large current-sense voltages. the combined volt- age across q4 and r2 can cause d2 to conduct. if very large sense voltages are used, connect d2 directly from q4 s source to drain. forced-pwm mode buck1 and buck2 operate in forced-pwm mode when skp1/ sdn and skp2/ sdn are unconnected. the low-noise forced-pwm mode disables the zero-cross- ing comparator, allowing the inductor current to reverse at light loads. this causes the low-side gate-drive waveform to become the complement of the high-side gate-drive waveform. this in turn causes the inductor current to reverse at light loads while dh_ maintains a duty factor of v out_ /v in . the benefit of forced-pwm mode is to keep the switching frequency fairly constant, but it comes at a cost: the no-load 5v bias supply cur- rent can be 20ma to 80ma total for both buck1 and buck2, depending on the external mosfets and switching frequency. forced-pwm mode is most useful for reducing audio- frequency noise, improving load-transient response, providing sink-current capability for dynamic-output voltage adjustment, and improving the cross-regulation of multiple-output applications that use a flyback trans- former or coupled inductor. buck1 uses pwm mode during all output transitions, while the slew-rate con- troller is active and for 32 clock cycles thereafter. automatic pulse-skipping mode in skip mode (skp_/ sdn = high), an inherent automatic switchover to pfm takes place at light loads. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current s zero crossing. this mechanism causes the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between con- tinuous and discontinuous inductor-current operation (also known as the critical conduction point). in low duty-cycle applications, this threshold is relative- ly constant, with only a minor dependence on battery voltage. where k is the on-time scale factor (table 3). the load current level at which pfm/pwm crossover occurs, i load(skip) , is equal to 1/2 the peak-to-peak ripple cur- rent, which is a function of the inductor value (figure 7). for example, in the standard application circuit with k = 3.3s (table 3), v out1 = 1.25v, v in = 12v, and l1 = 0.68h, switchover to pulse-skipping operation occurs at i load1 = 2.7a. the crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. the switching waveforms can appear noisy and asyn- chronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-tran- sient response, especially at low-input-voltage levels. i kv l vv v load skip out in out in _( ) __ _ = ? 2
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 31 dc output accuracy specifications for buck2 refer to the threshold of the error comparator. when the induc- tor is in continuous conduction, buck2 output voltage has a dc regulation level higher than the trip level by 50% of the ripple. in discontinuous conduction (skp2/ sdn = high, light-loaded), buck2 output volt- age has a dc regulation level higher than the error- comparator threshold by approximately 1.5% due to slope compensation. note that buck1 automatically enters forced-pwm mode during all output voltage transitions and stays in forced-pwm mode until the transition is completed and for 32 clock cycles thereafter. the reason for that is the forced-pwm operation provides current sinking capa- bility required during output-voltage transitions. linear-regulator controller the linear-regulator controller of the MAX1816/max1994 is an analog gain block with an open-drain n-channel output. it drives an external pnp pass transistor with a 220 ? base-to-emitter resistor (figure 1). the controller is guaranteed to provide at least 20ma sink current. the linear regulator is typically used to provide a 1.2v/500ma vid logic supply. the controller is designed to be stable with an output capacitor of 10f or more. the output voltage can be adjusted with a resistive volt- age-divider between the linear regulator output and analog ground with the center tap connected to linfb. the set point of linfb is 1.0v. the regulator is enabled when lin/ sdn is high. as soon as linfb is in regula- tion, the open-drain power-good output lingood goes high after a 1ms (min) delay. when the output goes out of regulation or lin/ sdn goes low, lingood is forced low within approximately 10s. the 1ms (min) lingood delay is necessary to allow the plls in the cpu to power up and stabilize before turning on the main regulator. the delay time is com- puted based on 1024 r time clock cycles. as such, the delay varies based on the r time period. mosfet gate drivers (dh_, dl_) the dh_ and dl_ drivers are optimized for driving mod- erate-sized high-side and larger low-side power mosfets. this is consistent with the low duty factor seen in the notebook cpu environment, where a large v in -v out _ differential exists. two adaptive dead-time circuits monitor the dh_ and dl_ outputs and prevent the opposite side fet from turning on until dl_ or dh_ is fully off. there must be a low-resistance, low-inductance path from the dl_ and dh_ drivers to the mosfet gates for the adaptive dead-time circuits to work properly. otherwise, the sense circuitry in the MAX1816/max1994 interprets the mosfet gate as off while there is actual- ly still charge left on the gate. use very short, wide traces measuring 10 to 20 squares (50 mils to 100 mils wide if the mosfet is 1in from the MAX1816/max1994). the internal pulldown transistor that drives dl_ low is robust, with a very low pulldown resistance. for dl1, this resistance is 0.35 ? (typ), while the resistance for dl2 is slightly higher at 0.7 ? (typ). this helps prevent dl_ from being pulled up during the fast rise-time of the inductor node, due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier mosfet. however, for high-current applications, some combinations of high- and low-side fets can cause excessive gate-drain coupling, which can lead to effi- ciency-killing, emi-producing shoot-through currents. this is often remedied by adding a resistor in series with bst_, which increases the turn-on time of the high- side fet without degrading the turn-off time (figure 8). lx_ +5v v batt 5 ? typ dh_ bst_ MAX1816 max1994 figure 8. reducing the switching-node rise time inductor current i load = i peak /2 on-time 0 time i peak l v batt - v out ? i ? t = figure 7. pulse-skipping/discontinuous crossover point
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 32 ______________________________________________________________________________________ shutdown control (skp1/ s s d d n n , skp2/ s s d d n n , and lin/ s s d d n n ) if buck2 is used, always start buck2 before starting buck1. when skp1/ sdn goes below 0.5v, buck1 enters low-power shutdown mode. pgood goes low immediately. the output voltage ramps down to zero in 25mv steps at the clock rate set by r time . thirty-two clocks after the dac reaches the zero setting, dl1 is forced to v dd , and dh1 is forced low. when skp1/ sdn goes above 1.4v or floats, the dac target is evaluated and switching begins. the slew-rate controller ramps up from zero in 25mv steps to the selected dac code value. there is no traditional soft-start (variable current- limit) circuitry, so full output current is available immedi- ately. floating skp1/ sdn causes buck1 to operate in low-noise forced-pwm mode. forcing skp1/ sdn above 2.8v enables skip mode operation. when skp2/ sdn goes below 0.5v, buck2 enters shut- down mode. in shutdown mode, dl2 is forced to v dd if overvoltage protection is enabled. if ovpset is con- nected to v cc , overvoltage protection is disabled and dl2 is forced low in shutdown mode. when lin/ sdn goes below 0.8v, the linear regulator of the MAX1816/max1994 enters shutdown mode. in shutdown mode, linbse is forced to a high-impedance state preventing sufficient drive to the external pnp pass transistor in the regulator. lingood is forced low within 10s (typ) when lin/ sdn goes low. forcing lin/ sdn above 2.4v turns on the linear regulator. power-on reset power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and preparing the MAX1816/max1994 for operation. v cc undervoltage lockout (uvlo) circuitry inhibits switching, forces pgood low, and forces the dl1 gate driver high (to enforce output overvoltage protection). the dl2 gate driver is also forced high if ovp is enabled. when v cc rises above 4.25v, the dac inputs are sampled and the output voltage begins to slew to the dac setting. for automatic startup, the battery voltage should be present before v cc . if the MAX1816/max1994 attempt to bring the output into regulation without the battery voltage present, the fault latch will trip. toggling any of the shut- down control pins resets the fault latch. power valid outputs (pgood and lingood) pgood is an open-drain power-good output. table 4 describes the behavior of pgood with respect to the logic inputs. window comparators on fbs and out2 (fb2) control the pgood output. if buck1 and buck2 are in regulation then pgood is high, except during power-up and power-down. the pgood output goes low if fbs or out2 (fb2) is outside a window of 10% about the nominal set point (see the dac inputs and internal multiplexers and adjusting buck2 output voltage sections). pgood is forced low when skp1/ sdn is low. if skp2/ sdn is low, then out2 (fb2) does not affect pgood. normally, pgood is forced high during all vid transitions, and stays high for 4 clock periods after the dac count is equalized. if buck2 goes out of regu- lation during these conditions, then pgood goes low as a consequence. a pullup resistor on pgood caus- es additional finite shutdown current. the following conditions must all be met for pgood to go high: v cc must be above uvlo. skp1/ sdn must be greater than 1.4v or unconnected. the output of buck1 must be within a window of 10% about the nominal set point. pgood is forced high during dac code transitions of buck1. the blanking period persists for n+4 r time clock cycles. blanking does not occur during power-up and power-down. if skp2/ sdn is not low, then out2 (fb2) must be within a window of 10% about the nominal set point. when enabled, a fault on out2 overrides the blank- ing on buck1. lingood is an open-drain power-good output for the linear regulator. lingood goes high at least 1ms after the internal comparator signals that the output is in reg- ulation. in normal operation, if the internal comparator signals that the circuit is out of regulation, lingood goes low within approximately 10s (typ). if lin/ sdn goes low, lingood is immediately forced low. note that all three regulators are forced off when a fault is detected. dl_ are forced high, dh_ are forced low, and the linear regulator is turned off. (see the output overvoltage protection, output undervoltage protection, uvlo, and thermal fault protection sections). dac inputs and internal multiplexers (sus) the MAX1816/max1994 have a unique internal vid input multiplexer (mux) that can select one of two different vid dac code settings for different processor states. when the logic level at sus is low, the mux selects the vid dac code settings from the d0 d4 inputs (table 5). do not leave d0 d4 floating use 100k ? pullup resistors if the inputs float. when sus is high, the suspend mode mux selects the vid dac code settings from the s0/s1 input decoder. the outputs of the decoder are determined by
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 33 table 4. buck1 and buck2 operating mode truth table ovp skp1/ sdn skp2/ sdn dl1 dl2 mode pgood x gnd v cc high switching buck2 low enabled v cc gnd switching high buck1 monitor buck1 only disabled v cc gnd switching low buck1 monitor buck1 only enabled gnd gnd high high shutdown low disabled gnd gnd high low shutdown low xv cc v cc switching switching both in skip mode monitor both enabled >10.8v gnd switching high buck1 no-fault test mode monitor buck1 only disabled >10.8v gnd switching low buck1 no-fault test mode monitor buck1 only x >10.8v v cc switching switching no-fault test mode monitor both x >10.8v float switching switching in forced pwm mode no-fault test mode monitor both enabled float gnd switching in forced pwm mode high buck1 in forced pwm mode monitor buck1 only disabled float gnd switching in forced pwm mode low buck1 in forced pwm mode monitor buck1 only x float v cc switching in forced pwm mode switching buck1 in forced pwm mode, buck2 in skip mode monitor both x float float switching in forced pwm mode switching in forced pwm mode buck1 and buck2 in forced pwm mode monitor both x gnd float high switching in forced pwm mode buck1 off, buck in forced pwm mode low xv cc float switching switching in forced pwm mode buck1 in skip mode, buvk2 in forced pwm mode monitor both enabled v cc or float v cc or float high high ovp and uvp faults low disabled v cc or float v cc or float high high uvp faults only low x = don t care. inputs s0 and s1, which are four-level digital inputs (table 6). all code transitions (even those asking for the exact same code) activate the slew-rate controller. in other words, up-going or down-going transitions from one code to another, soft-start and soft-stop are all handled in the same way. buck1 output-voltage offset control (sus, perf, d d p p s s l l p p , , and ofs_) the MAX1816/max1994 support three independent off- sets to the voltage-positioned load line. the offsets are adjusted using resistive voltage-dividers at the ofs0 ofs2 inputs (see figure 10). for inputs from 0 to 0.8v, a negative offset is added to the output that is
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 34 ______________________________________________________________________________________ equal to 1/8th the voltage appearing at the selected ofs input ( ? v out = -0.125 v ofs_ ). for inputs from 1.2v to 2v, a positive offset is added to the output that is equal to 1/8th the difference between the reference voltage and the voltage appearing at the selected ofs input ( ? v out = 0.125 (v ref - v ofs_ )). with this scheme, both positive and negative offsets can be achieved with a single voltage-divider. the piecewise linear transfer function is shown in figure 9. the regions of the transfer function below zero, above 2.0v, and between 0.8v and 1.2v are undefined. ofs inputs are disallowed in these regions, and the respec- tive effects on the output are not specified. the offset control inputs are selected using a combina- tion of the three logic inputs (sus, perf, and dpslp ), which also define the operating mode for the MAX1816/max1994. table 7 details which ofs input is selected based on these control inputs. buck1 output-voltage transition timing the MAX1816/max1994 are designed to perform out- put voltage transitions in a controlled manner, automati- cally minimizing input surge currents. this feature allows the regulator to perform nearly ideal transitions, guaranteeing just-in-time arrival at the new output volt- age level with the lowest possible peak currents for a given output capacitance. modern mobile cpus operate at multiple clock frequen- cies that require multiple vid settings. it is common when transitioning from one clock frequency to another for the cpu to go into a low-power state before chang- ing the output voltage and clock frequency. the change must be accomplished within a fixed time interval often less than 100s. table 6. output voltage vs. suspend mode dac codes s1 s0 v out (v) MAX1816/max1994 gnd gnd 1.075 gnd ref 1.050 gnd open 1.025 gnd v cc 1.000 ref gnd 0.975 ref ref 0.950 ref open 0.925 ref v cc 0.900 open gnd 0.875 open ref 0.850 open open 0.825 open v cc 0.800 v cc gnd 0.775 v cc ref 0.750 v cc open 0.725 v cc v cc 0.700 table 5. output voltage vs. dac codes d4 d3 d2 d1 d0 v out (v) MAX1816 v out (v) max1994 0 0 0 0 0 1.750 2.000 0 0 0 0 1 1.700 1.950 0 0 0 1 0 1.650 1.900 0 0 0 1 1 1.600 1.850 0 0 1 0 0 1.550 1.800 0 0 1 0 1 1.500 1.750 0 0 1 1 0 1.450 1.700 0 0 1 1 1 1.400 1.650 0 1 0 0 0 1.350 1.600 0 1 0 0 1 1.300 1.550 0 1 0 1 0 1.250 1.500 0 1 0 1 1 1.200 1.450 0 1 1 0 0 1.150 1.400 0 1 1 0 1 1.100 1.350 0 1 1 1 0 1.050 1.300 0 1 1 1 1 1.000 no cpu 1 0 0 0 0 0.975 1.275 1 0 0 0 1 0.950 1.250 1 0 0 1 0 0.925 1.225 1 0 0 1 1 0.900 1.200 1 0 1 0 0 0.875 1.175 1 0 1 0 1 0.850 1.150 1 0 1 1 0 0.825 1.125 1 0 1 1 1 0.800 1.100 1 1 0 0 0 0.775 1.075 1 1 0 0 1 0.750 1.050 1 1 0 1 0 0.725 1.025 1 1 0 1 1 0.700 1.000 1 1 1 0 0 0.675 0.975 1 1 1 0 1 0.650 0.950 1 1 1 1 0 0.625 0.925 1 1 1 1 1 0.600 no cpu
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 35 at the beginning of an output voltage transition, the regu- lator is placed in forced-pwm mode and the pgood output is high. if there is a fault on buck2 during this period, pgood goes low. the output voltage follows the internal dac code, which changes in 25mv increments until it reaches the programmed vid code. the regulator remains in forced-pwm mode for 32 clock cycles after the transition to ensure that the output settles properly. the pgood output is forced high for 4 clock cycles after the transition also to allow the output to settle. the slew- rate clock frequency (set by the r time resistor) must be set fast enough to ensure that the longest transition is completed within the allotted time interval. the output voltage transition is performed in 25mv steps, preceded by a 4s delay and followed by one additional clock period. the total time for a transition depends on r time , the voltage difference, and the accuracy of the MAX1816/max1994s slew-rate clock, and is not depen- dent on the total output capacitance. the greater the out- put capacitance, the higher the surge current required for the transition. the MAX1816/max1994 automatically control the current to the minimum level required to com- plete the transition in the calculated time. as long as the surge current is less than the current limit set by ilim1, the transition time is given by: where f slew = 252khz 143k ? / r time , v old is the original dac setting, and v new is the new dac setting. see time frequency accuracy in the electrical characteristics table for f slew accuracy. the practical range of r time is 68k ? to 680k ? , corresponding to 1.9s to 19s per 25mv step. although the dac takes discrete 25mv steps, the output filter makes the transi- tions relatively smooth. the average inductor current required to make an output voltage transition is: i l ? c out ? 25mv ? f slew the slew-rate controller also performs a soft-start and soft-stop function. the soft-start function works by counting up from zero, in order to minimize turn-on surge currents. the soft-stop executes this process in reverse, eliminating the negative output voltages and the need for an external schottky output clamp diode that would otherwise be required if dl1 were simply forced high. setting buck2 output voltage buck2 s dual mode operation allows the selection of common voltages without requiring external compo- nents (figure 1). in fixed mode, connect fb2 to agnd for 2.5v output, or connect fb2 to v cc for 1.8v output. in adjustable mode, the output voltage can be adjusted from 1.0v to 5.5v using a resistive voltage-divider from the buck2 output to agnd with the center tap con- nected to fb2 (figure 11). the equation for adjusting the output voltage is: where v fb2 is 1.0v. vv r r out fb 22 1 1 2 =+ ? ? ? ? ? ? ts f vv mv slew slew old new ?+ + ? ? ? ? ? ? ? ? ? ? ? ? ? 4 1 1 25 figure 9. offset-control transfer function -0.15 -0.05 -0.10 0.05 0 0.10 0.15 undefined 0 1.0 0.5 0.8 1.2 1.5 2.0 ofs_ input voltage (v) output offset voltage (v) figure 10. simplified offset-control circuits ref or v out1 ref or v out1 or ofs0 ofs1 ofs1 ofs0 ofs1 ofs2 dual mode is a trademark of maxim integrated products, inc.
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 36 ______________________________________________________________________________________ output overvoltage protection output overvoltage protection (ovp) is available on buck1, buck2, and the linear regulator. the linfb input is always monitored for overvoltage. the fbs and out2 inputs are only monitored for overvoltages when ovp is enabled. when any output exceeds the desired ovp threshold, the fault latch is set and the regulator is turned off. in the fault mode, dl1 and dl2 are forced high, dh1 and dh2 are forced low, and the linear regu- lator is turned off. for buck1 and buck2, if the condi- tion that caused the overvoltage (such as a shorted high-side mosfet) persists, the battery fuse will blow. dl1 is also kept high continuously when v cc uvlo is active, as well as in shutdown mode (table 4). the device remains in the fault mode until v cc is cycled, or either skp_/ sdn or lin/ sdn is toggled. the triggering of the reset condition occurs on the rising edge of the skp_/ sdn or lin/ sdn signals. for buck1, the default ovp threshold is 2v for the MAX1816 and 2.25v for the max1994. for buck2, the ovp threshold is 115% of the nominal voltage for out2 (fb2 if external feedback is used for buck2). the over- voltage detection level for fbs can be adjusted through an external resistive voltage-divider. connecting ovpset to a voltage between 1.0v and 2.0v sets the ovp thresh- old for fbs. for the MAX1816, the fault latch is set when v fbs > v ovpset . for the max1994, the fault latch is set when v fbs > 1.125 ? v ovpset . the ovp threshold on out2 is not adjustable and remains at the default value of 115%. connecting ovpset to v cc disables ovp for buck1 and buck2. the operation of the linear regulator is not affected by ovpset. overvoltage protection can be disabled using the no fault test mode (see the no fault test mode section). output undervoltage protection the output undervoltage protection (uvp) is available on buck1, buck2, and the linear regulator. the protection is similar to foldback current limiting, but employs a timer rather than a variable current limit. if the output voltage is under 70% of the nominal value for buck1 and buck2, and under 90% for the linear regulator (see the electrical characteristics table for the respective uvp thresholds), the fault latch is set. in the fault mode, dl1 and dl2 are forced high, dh1 and dh2 are forced low, and the linear regulator is turned off. the controller does not restart until v cc power is cycled, or either skp_/ sdn or lin/ sdn is toggled. the triggering of the reset condition occurs on the rising edge of the skp_/ sdn or lin/ sdn signals. table 7. offset selection truth table inputs active ofs inputs mode sus perf dpslp ofs2 ofs1 ofs0 battery sleep 0 0 0 1 0 0 battery 0 0 1 0 1 0 performance sleep 0 1 0 0 0 1 performance 0 1 1 0 0 0 suspend 1 0 0 0 0 0 suspend 1 0 1 0 0 0 suspend 1 1 0 0 0 0 suspend 1 1 1 0 0 0 0 = logic low or input not selected. 1 = logic high or input selected. dl2 agnd out2 cs2 dh2 fb2 v batt v out r1 r2 MAX1816 max1994 pgnd figure 11. adjusting buck2 output voltage with a resistive voltage-divider
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 37 to allow startup, uvp is ignored during the undervoltage blanking time (the first 256 cycles of the slew rate after startup for buck1, the first 4096 cycles for buck2 and the first 512 cycles for the linear regulator). uvp can be disabled using the no fault test mode (see the no fault test mode section). uvlo the MAX1816/max1994 provide input undervoltage lock- out (uvlo) protection. if the v cc voltage drops low enough to trip the uvlo comparator, it is assumed that there is not enough supply voltage to make valid deci- sions. in order to protect the output from overvoltage faults, dl1 and dl2 are forced high if ovp is enabled, dh_ is forced low, and the linear regulator is turned off. if ovp is disabled, dl1 is forced high, dl2 is forced low, dh_ is forced low, and the linear regulator is turned off. for buck1 (and also for buck2 if ovp is enabled), this condition rapidly forces the outputs to zero since the slew-rate controller is not active. the fault results in large negative inductor currents and possibly small negative output voltages. if v cc is likely to drop in this fashion, the outputs can be clamped with schottky diodes to pgnd to reduce the negative excursions. thermal fault protection the MAX1816/max1994 feature a thermal fault-protec- tion circuit. when the junction temperature rises above +160 c, a thermal sensor sets the fault latch, which pulls dl_ high, dh_ low, and turns off the linear regula- tor. the device remains in fault mode until the junction temperature cools by 15 c, and either v cc power is cycled, or skp_/ sdn or lin/ sdn is toggled. no fault test mode the over/undervoltage protection features can compli- cate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. therefore, a test mode is provided to disable the ovp, uvp, and thermal shut- down features, and clear the fault latch if it has been set. test mode applies to buck1, buck2, and the lin- ear regulator. in the test mode, buck1 operates as if skp1/ sdn was high (skip mode). set the voltage on skp1/ sdn between 10.8v to 13.2v to enable the no fault test mode. buck1/buck2 design procedure firmly establish the input voltage range and maximum load current for buck1 and buck2 before choosing a switching frequency and inductor operating point (rip- ple-current ratio). the primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: 1) input voltage range. the maximum value (v in(max) ) must accommodate the worst-case high ac adapter voltage. the minimum value (v in(min) ) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selec- tor switches. if there is a choice, lower input volt- ages result in better efficiency. 2) maximum load current. there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continu- ous load current (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-con- tributing components. modern notebook cpus gen- erally exhibit i load = i load(max) ? 80%. 3) switching frequency. this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are proportional to frequency and v in . the optimum frequency is also a moving target, due to rapid improvements in mosfet technology that are mak- ing higher frequencies more practical. 4) inductor operating point. this choice provides tradeoffs between size and efficiency. low inductor values cause large ripple currents, resulting in the smallest size, but poor efficiency and high output noise. the minimum practical inductor value is one that causes the circuit to operate at the edge of criti- cal conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size- reduction benefit. the MAX1816/max1994s pulse- skipping algorithm initiates skip mode at the critical conduction point. so, the inductor operating point also determines the load current value at which pfm/pwm switchover occurs. the optimum point is usually found between 20% and 50% ripple current.
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 38 ______________________________________________________________________________________ 5) inductor ripple current. the inductor ripple cur- rent also impacts transient response performance, especially at low v in - v out differentials. low induc- tor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time: where t off(min) is the minimum off-time (see the electrical characteristics table) and k is from table 3. inductor selection the switching frequency and operating point (% ripple current or lir) determine the inductor value as follows: example: i load(max) = 19a, v in = 7v, v out = 1.25v, f sw = 300khz, 30% ripple current or lir = 0.30: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak induc- tor current (i peak ): setting the current limit for buck1 connect ilim1 to v cc for a default 50mv (cs1+ to cs1-) current-limit threshold. for an adjustable threshold, con- nect a resistive voltage-divider from ref to gnd, with ilim1 connected to the center tap. the current-limit threshold is precisely 1/10th of the voltage at ilim1. when adjusting the current limit, use 1% tolerance resistors for the divider and a 10a divider current to prevent a signifi- cant increase of errors in the current-limit threshold. the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half of the ripple current; therefore: the current-sense resistor value (r1 in figure 1) is cal- culated according to the worst-case (minimum) current- limit threshold voltage (see the electrical characteristics table) and the valley current-limit threshold i limit(min) described above: where 0.8 is a factor for the worst-case low current-limit threshold. to protect against component damage during short-cir- cuit conditions, use the calculated value of r sense to size the mosfet switches and specify inductor satura- tion-current ratings according to the worst-case high current-limit threshold: where 1.2 is a factor for worst-case high current-limit threshold. low-inductance resistors, such as surface-mount metal film, are recommended. setting the current limit for buck2 connect ilim2 to v cc for a default 50mv cs2 to gnd current-limit threshold. for an adjustable threshold, connect a resistive voltage-divider from ref to gnd, with ilim2 connected to the center tap. the current- limit threshold is precisely 1/10th of the voltage at ilim2. when adjusting the current limit, use 1% toler- ance resistors for the divider and a 10a divider cur- rent to prevent a significant increase of errors in the current-limit threshold. i mv r lir fixed mode i v r lir adjustable mode peak max sense peak max ilim sense () () . () () .. () () = + = + 50 1 2 1 01 12 1 1 r mv i fixed mode r v i adjustable mode sense limit min sense ilim limit min = = 50 0 8 01 08 1 . () .. () () () ii lir limit min load max () ( ) > ? ? ? ? ? ? ? 1 2 ii lir peak load max =+ ? ? ? ? ? ? () 1 2 l vv v v khz a h = = ? 125 7 125 7 300 0 30 19 060 .(.) . . l vvv v f lir i out in out in sw load max = ? () () v ii lk v v t cv k vv v t sag load load out in off min out out in out in off min = + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () () () 12 2 2
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 39 the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half of the ripple current; therefore: where i limit(min) equals the minimum current-limit threshold voltage divided by the current-sense resistor. the sense resistor (r2 in figure 1) determines the achiev- able current-limit accuracy. there is a trade-off between current-limit accuracy and sense-resistor power dissipa- tion. most applications employ a current-sense voltage of 50mv to 100mv. choose a sense resistor so that: where 0.8 is a factor for worst-case low current-limit threshold. extremely cost-sensitive applications that do not require high-accuracy current sensing can use the on-resis- tance of the low-side mosfet switch in place of the sense resistor by connecting cs2 to lx2. use the worst- case maximum value for r ds(on) from the mosfet data sheet taking into account the rise in r ds(on) with temperature. a good general rule is to allow 0.5% addi- tional resistance for each c temperature rise. assume the current-sense resistor in the application cir- cuit in figure 1 is removed and cs2 is directly tied to lx2. the q4 maximum r ds(on) = 3.8m ? at t j = +25 c and 5.7m ? at t j = +125 c. the minimum current-limit threshold is: and the required valley current limit is: i limit(min) > 7a ? (1 - 0.30/2) = 5.95a since 7a is greater than the required 5.95a, the circuit can deliver the 7a full-load current. output capacitor selection (buck1 and buck2) the output filter capacitor must have low enough effec- tive series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. also, the capacitance value must be high enough to absorb the inductor ener- gy going from a full-load to no-load condition without tripping the ovp circuit. in cpu core voltage regulators and other applications where the output is subject to violent load transients, the output capacitor s size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in non-cpu applications, the output capacitor s size often depends on how much esr is needed to maintain an acceptable level of output-voltage ripple: the actual microfarad capacitance value required often relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and volt- age rating rather than by capacitance value (this is true of tantalums, oscons, and other electrolytics). when using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually deter- mined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. the amount of overshoot due to stored inductor energy can be calculated as: where i peak is the peak inductor current. v li cv soar peak out out = 2 2 r v lir i esr pp load max ? () r v i esr dip load max () i mv m a limit min () .. . = = 500 01 08 57 7 ? r mv i fixed mode r v i adjustable mode sense limit min sense ilim limit min = = 50 0 8 01 08 2 . ( ) .. ( ) () () ii lir limit min load max () ( ) > ? ? ? ? ? ? ? 1 2
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 40 ______________________________________________________________________________________ buck1 stability considerations buck1 is fundamentally different from previous quick- pwm controllers in two respects: it uses a current-sense amplifier to obtain the current feedback signal (ramp), and it uses differential remote sense to compensate for voltage drops along the high-current path. the regulator adds the differential remote-sense signal to the current- feedback signal to correct the output voltage. as long as the amplitude of the resulting signal is greater than 1% of the output voltage, the regulator remains stable. stability can be determined by comparing the zero formed with the current-sense feedback network to the switching frequency. the boundary condition of stability is given by the fol- lowing expression: where c out1 is the local output capacitance (figure 1), c remote is the remote output capacitance, r local is the esr of the local capacitors, r remote is the esr of the remote capacitors, and r droop is the effective voltage-positioning resistance, which is determined by the voltage-positioning gain a vps and current-sense resistor r sense : r droop = a vps x r sense like previous quick-pwm controllers, larger values of esr and sense resistance increase stability. the volt- age-positioning gain a vps effectively increases the sense resistance, which further enhances stability. the rc time constants of the local and remote capaci- tors affect the stability criteria. these two time con- stants are defined as follows: local = (r droop + r local + r pcb_trace ) x c out1 remote = (r droop + r remote ) x c remote where r pcb _ trace is the pc board trace resistance shown in figure 1. when the local capacitance time constant is either much greater or much smaller than that of the remote capacitance, the stability criteria is: in applications where these two time constants are approximately equal, the criteria for stable operation reduces to: the standard application circuit (figure 1) operating at 300khz easily achieves stable operation because the time constant of the local capacitors is much greater than that of the remote capacitors. in this example, c out1 = 990f, r local = 3.3m ? , c remote = 10f, r remote = 5m ? , and r droop = 2 x 1m ? = 2m ? : when voltage positioning is not used (a vps = 0) and the esr of the output capacitors alone cannot meet the sta- bility requirement, the current feedback signal must be generated from a different source. the current ramp sig- nal at cs1+ and the output voltage must be summed at the fbs input. for stable operation, a 3.3f feed-for- ward capacitor is added from the cs1+ input to fbs and a 10 ? resistor is inserted from the remote load to fbs forming an rc filter (figure 12). the cutoff frequen- cy of the rc filter should be approximately an order of magnitude lower than the regulator s switching frequen- cy to prevent sluggish transient response. to avoid input-bias current-induced offset errors, the resistor should be less than 20 ? . 2 990 10 3 3 990 5 10 1 2 300 532 167 mffm fm f khz ss ?? ? + () + + ? ? ? . . . rr c f and rr c f droop local out sw droop remote remote sw + () + () 1 1 2 1 2 rcc r cr c f droop out remote local out remote remote sw + () + + 1 1 1 2 f rcc rcr c z droop out remote local out remote remote + () + + ? ? ? ? ? ? ? ? 1 2 1 1 f f z sw
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 41 for nonvoltage-positioned applications using a feed- forward circuit, the rc time constants of the local and remote capacitors are defined as: local = (r sense + r local ) x c out1 remote = (r sense + r remote + r pcb_trace ) x c remote the new stability criteria for nonvoltage-positioned applications using feed forward becomes: for local much greater or much smaller than remote , and when local and remote are approximately equal. if the voltage-positioning gain in the standard applica- tion circuit (figure 1) is set to zero and the feed-forward compensation circuit shown in figure 12 is used, stable operation can still be easily achieved. in this example, c out1 = 990f, r local = 3.3m ? , c remote = 10f, r remote = 5m ? , r sense = 1m ? , and r pcb _ trace = 2m ? , and the local time constant is much greater than the remote time constant. therefore: unstable operation manifests itself in two related but distinctly different ways: double-pulsing and fast-feed- back loop instability. double-pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output-voltage signal. this fools the error comparator into triggering a new cycle immediately after the 400ns minimum off- time period has expired. double-pulsing is more annoy- ing than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability, which is caused by insufficient current feedback signal. loop instability can result in oscillations at the output after line or load perturbations that can trip the overvolt- age protection latch or cause the output voltage to fall below the tolerance limit. the easiest method for check- ing stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage rip- ple envelope for overshoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. buck2 stability considerations the stability criterion for buck2 is the same as previous quick-pwm controllers like the max1714. stability is determined by comparing the value of the esr zero to the switching frequency. the point of stability is given by the following expression: for good phase margin, it is recommended to increase the equivalent rc time constant by a factor of two. the standard application circuit (figure 1) operating at 390khz with c out = 330f and r esr = 10m ? , easily meets this requirement. f f where f rc esr sw esr esr out = 1 2 1 990 10 3 3 990 5 10 1 2 300 432 167 mffm fm f khz ss ?? ? + () + + ? ? ? . . . rr c f and rr c f sense local out sw sense remote remote sw + () + () 1 1 2 1 2 rcc r cr c f sense out remote local out remote remote sw + () + + 1 1 1 2 figure 12. output feed forward for nonvoltage-positioned applications c out r sense 3.3 f 10 ? pc board trace resistance remote load cs1+ cs1- fbs gds pc board trace resistance
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 42 ______________________________________________________________________________________ input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents defined by the following equation: the rms input currents for buck1 and buck2 can be calculated using the above equation. use the sum of these two currents as the total rms current. note that this is a very conservative estimation because the two regulators are never in phase 100% of the time. the actual rms current is always lower than the calculated value. for most applications, nontantalum chemistries (ceramic or oscon) are preferred due to their resilience to inrush surge currents typical of systems with a switch or a connector in series with the battery. if the MAX1816/max1994 operate as the second stage of a two-stage power conversion system, tantalum input capacitors are acceptable. in either configuration, choose an input capacitor that exhibits less than +10 c temperature rise at the rms input current for optimal circuit longevity. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability (>12a) when using high-voltage (>20v) ac adapters. low-current applications usually require less attention. the high-side mosfet (q1 in figure1) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . calculate both of these sums. ideally, the losses at v in(min) should be roughly equal to the losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly high- er than the losses at v in(max) , consider increasing the size of q1. conversely, if the losses at v in(max) are sig- nificantly higher than the losses at v in(min) , consider reducing the size of q1. if v in does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. choose a low-side mosfet (q2) that has the lowest possible r ds(on) , comes in a moderate-sized package (i.e., two or more 8-pin sos, dpaks, or d 2 paks), and is reasonably priced. ensure that the MAX1816/max1994 dl_ gate driver can drive q2; in other words, check that the dv/dt caused by q1 turning on does not pull up the gate of q2 due to drain-to-gate capacitance, causing cross-conduction problems. switching losses are not an issue for the low-side mosfet, since it is a zero-voltage switched device when used in the buck topology. mosfet power dissipation the high-side mosfet conduction power dissipation due to on-state channel resistance is: generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissipation limits often constrains how small the mosfet can be. switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the cv 2 f sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when subjected to v in(max) , reconsider the mosfet selection. calculating the power dissipation in q1 due to switch- ing losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn- off times. these factors include the internal gate resis- tance, gate charge, threshold voltage, source induct- ance, and pc board layout characteristics. the follow- ing switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation and thermal measurements: where c rss is the reverse transfer capacitance of q1 and i gate is the peak gate-drive source/sink current (1.5a typ for buck1, 0.75a typ for buck2). for the low-side mosfet (q2), the worst-case power dissipation always occurs at maximum battery voltage: the worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exceed the current limit and cause the fault latch to trip. to protect against this possibility, overdesign the circuit to tolerate: i load =i limit(high ) + (lir/2) ? i load(max) pd q v v ir out in max load ds on () () () 21 2 2 = ? ? ? ? ? ? ? pd q switching cv fi i rss in max sw load gate (_ ) () 1 2 = pd q conduction v v ir out in load ds on (_ ) () 1 2 1 = ii vvv v rms load out in out in = ? ()
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 43 where i limit(high) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. the mosfets must have a good-sized heat sink to handle the overload power dissipation. if short-circuit protection without overload protection is enough, a normal i load value can be used for calculating compo- nent stresses. choose a shottky diode (d1) having a forward voltage low enough to prevent the q2 mosfet body diode from turning on during the dead time. as a general rule, a diode having a dc current rating equal to 1/3 of the load current is sufficient. this diode is optional and can be removed if efficiency is not critical. linear regulator design procedure output voltage selection adjust the linear regulator s output voltage by connect- ing a resistive voltage-divider from v lin to agnd with the center tap connected to linfb (figure 1). select r9 in the range of 10k ? to 100k ? . calculate r8 with the following equation: r8 = r9 [(v lin / 1.00v) - 1] pass transistor selection the pnp pass transistor must meet specifications for current gain (h fe ), input capacitance, emitter-collector saturation voltage, and power dissipation. the transistor s current gain limits the guaranteed maximum output current to: where i drv is the minimum base-drive current, and r eb is the pullup resistor connected between the transis- tor s emitter and base. furthermore, the transistor s cur- rent gain increases the linear regulator s dc loop gain (see the linear regulator stability requirements sec- tion), so excessive gain destabilizes the output. therefore, transistors with current gain over 300a/a at the maximum output current are not recommended. the transistor s input capacitance and input resistance also create a second pole, which could be low enough to make the output unstable when heavily loaded. the transistor s saturation voltage at the maximum out- put current determines the minimum input-to-output voltage differential that the linear regulator supports. alternatively, the package s power dissipation could limit the usable maximum input-to-output voltage differ- ential. the maximum power dissipation capability of the transistor s package and mounting must exceed the actual power dissipation in the device. the power dissipation equals the maximum load current times the maximum input-to-output voltage differential: p = i load(max) x(v ldoin - v lin ) = i load(max) xv ce linear regulator stability requirements the MAX1816/max1994 linear-regulator controller uses an internal transconductance amplifier to drive an external pass transistor. the transconductance amplifi- er, the pass transistor, the emitter-base resistor, and the output capacitor determine the loop stability. if the output capacitor and pass transistor are not properly selected, the linear regulator is unstable. the transconductance amplifier regulates the output voltage by controlling the pass transistor s base cur- rent. since the output voltage is a function of the load current and load resistance, the total dc loop gain is approximately: where v t is 26mv at room temperature, i bias is the cur- rent though the emitter-base resistor (r eb ), and v ref = 1.0v. this bias resistor is typically 220 ? , providing approximately 3.2ma of bias current. the output capacitor and the load resistance create the dominant pole in the system. however, the pass tran- sistor s input capacitance creates a second pole in the system. additionally, the output capacitor s esr gener- ates a zero. to achieve stable operation, use the follow- ing equations to verify that the linear regulator is properly compensated: 1) first, determine the dominant pole set by the linear regulator s output capacitor and the load resistor: the unity gain crossover of the linear regulator is: f crossover =a v(ldo) f pole(cldo) 2) next, determine the second pole set by the emitter- base capacitance (including the transistor s input capacitance), the transistor s input resistance, and the emitter-base pullup resistor: f cr i cv pole cldo ldo load load max ldo ldo () () == 1 22 a v v ih i v ldo ref t bias fe load () . = ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? 155 ii v r h load max drv eb eb fe min () () = ? ? ? ? ? ? ?
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 44 ______________________________________________________________________________________ 3) a third pole is set by the linear regulator s feedback resistance and the capacitance between linfb and gnd, including the stray capacitance: 4) if the second and third poles occur well after unity gain crossover, the linear regulator remains stable: f pole(ceb) > 2f pole(cldo) a v(ldo) however, if the esr zero occurs before the unity gain crossover, cancel the zero with the feedback pole by changing circuit components such that: for most applications where ceramic capacitors are used, the esr zero always occurs after the crossover. output capacitor selection typically, more output capacitance provides the best performance, since this also reduces the output voltage drop immediately after a load transient. connect at least a 10f capacitor between the linear regulator s output and ground, as close to the external pass tran- sistor as possible. depending on the selected pass transistor, larger capacitor values may be required for stability (see the linear regulator stability requirements section). furthermore, the output capaci- tor s esr affects stability. use output capacitors with an esr less than 200m ? to ensure stability and optimum transient response. once the minimum capacitor value for stability is determined, verify that the linear regula- tor s output does not contain excessive noise. although adequate for stability, small capacitor values can pro- vide too much bandwidth, making the linear regulator sensitive to noise. larger capacitor values reduce the bandwidth, thereby reducing the regulator s noise sen- sitivity. applications information voltage positioning powering new mobile processors requires new tech- niques to reduce cost, size, and power dissipation. voltage positioning reduces the total number of output capacitors to meet a given transient response require- ment. setting the no-load output voltage slightly higher allows a larger step down when the output current sud- denly increases, and regulating at the lower output volt- age under load allows a larger step up when the output current suddenly decreases. allowing a larger step size means that the output capacitance can be reduced and the capacitor s esr can be increased. adding a series output resistor positions the full-load output voltage below the actual dac programmed volt- age. connect fb directly to the inductor side of the voltage-positioning resistor (r1, 1m ? ). the other side of the voltage-positioning resistor should be connected directly to the output filter capacitor with a short, wide pc board trace. with the gain pin floating (gain = 2), a 20a full-load current causes a 40mv drop in the output. this 40mv is a -3.2% droop. an additional benefit of voltage positioning is reduced power consumption at high load currents. because the output voltage is lower under load, the cpu draws less current. the result is lower power dissipation in the cpu, although some extra power is dissipated in r1. for a nominal 1.25v, 20a output, reducing the output voltage by 3.2% gives an output voltage of 1.21v and an output current of 19.4a. given these values, cpu power consumption is reduced from 25w to 23.5w. the additional power consumption of r1 is: 1m ? ? (19.4a) 2 = 0.38w and the overall power savings is as follows: 25w - (23.5w + 0.38w) = 1.12w in effect, 1.5w of cpu dissipation is saved, and the power supply dissipates some of the power savings, but both the net savings and the transfer of dissipation away from the hot cpu are beneficial. high-current master-slave applications the MAX1816/max1994 can be used in high-current applications using additional slave regulators. figure 2 illustrates a 40a master-slave application using this technique. the max1994 is placed in forced pwm mode to simplify operation with the slave. refer to the max1980 data sheet for a detailed description of the master-slave architecture and how to configure correctly the slave circuit. dropout performance the output voltage adjustment range for continuous- conduction operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot (375ns max at 550khz and 1000khz). for best dropout performance, use the slower (200khz) on-time settings. f cr pole fb ldo esr () 1 2 f crr pole fb fb () (||) = 1 289 f cr r ri vh crvh pole ceb eb eb in eb load t fe eb eb t fe () (||) == + 1 22
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 45 when working with low-input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. manufacturing tolerances and internal propaga- tion delays introduce an error to the ton k factor. this error is greater at higher frequencies (table 3). also, keep in mind that transient response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the v sag equation in the design procedure section). the absolute point of dropout is when the inductor cur- rent ramps down during the minimum off-time ( ? i down ) as much as it ramps up during the on-time ( ? i up ). the ratio h = ? i up / ? i down is an indicator of ability to slew the inductor current higher in response to increased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor current is less able to increase during each switching cycle and v sag greatly increases, unless additional output capacitance is used. a reasonable minimum value for h is 1.5, but this can be adjusted up or down to allow trade-offs between v sag , output capacitance, and minimum operating volt- age. for a given value of h, the minimum operating volt- age can be calculated as: where v drop1 and v drop2 are the parasitic voltage drops in the discharge and charge paths, respectively (see the on-time one-shot (ton) section), t off(min) is from the electrical characteristics table, and k is taken from table 3. the absolute minimum input volt- age is calculated with h = 1. if the calculated v in(min) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable v sag . if operation near dropout is anticipated, calculate v sag to be sure of adequate transient response. dropout design example v out = 1.2v f sw = 300khz k = 3.3s, worst-case k = 2.97s t off(min) = 500ns v drop1 = v drop2 = 100mv h = 1.5 calculate again with h = 1 gives the absolute limit of dropout: since 1.56v is less than the lower limit of the input volt- age range (2v), the practical minimum input voltage with reasonable output capacitance would be 2v. one-stage (battery input) vs. two-stage (5v input) conversion the MAX1816/max1994 can be used with a direct bat- tery connection (one stage) or can obtain power from a regulated 5v supply (two stage). each approach has advantages, and careful consideration should go into the selection of the final design. the one-stage approach offers smaller total inductor size and fewer capacitors overall due to the reduced demands on the 5v supply. the transient response of the single stage is better due to the ability to ramp up the inductor current faster. the total efficiency of a sin- gle stage is better than the two-stage approach. the two-stage approach allows flexible placement due to smaller circuit size and reduced local power dissipa- tion. the power supply can be placed closer to the cpu for better regulation and lower i 2 r losses from pc board traces. although the two-stage design has worse transient response than the single stage, this can be offset by the use of a voltage-positioned converter. ceramic output capacitor applications ceramic capacitors have advantages and disadvan- tages. they have ultra-low esr and are noncom- bustible, relatively small, and nonpolarized. they are also expensive and brittle, and their ultra-low esr char- acteristic can result in excessively high esr zero fre- quencies (affecting stability in nonvoltage-positioned circuits). in addition, their relatively low capacitance value can cause output overshoot when going abruptly from full-load to no-load conditions, unless the inductor value can be made small (high switching frequency), or there are some bulk tantalum or electrolytic capacitors in parallel to absorb the stored energy in the inductor. in some cases, there may be no room for electrolytic capacitors, creating a need for a dc-dc design that uses nothing but ceramic capacitors. v vv s s vv v in min () (. . ) . . .. . = + ? ? ? ? ? ? ? += ? ? 12 01 1 05 1 297 01 01 156 v vv s s vv v in min () (. . ) .. . .. . = + ? ? ? ? ? ? ? += ? ? 12 01 1 05 15 297 01 01 174 v vv th k vv in min out drop off min drop drop () () () = + ? ? ? ? ? ? ? ? ? +? 1 21 1
MAX1816/max1994 the MAX1816/max1994 can take full advantage of the small size and low esr of ceramic output capacitors in a voltage-positioned circuit. the addition of the posi- tioning resistor increases the ripple at fb, lowering the effective esr zero frequency of the ceramic output capacitor. output overshoot (v soar ) determines the minimum output capacitance requirement (see the output capacitor selection section). often the switching fre- quency is increased to 550khz or 1000khz, and the inductor value is reduced to minimize the energy trans- ferred from inductor to capacitor during load-step recovery. the efficiency penalty for operating at 550khz is about 2% to 3% and about 5% at 1000khz when compared to the 300khz voltage-positioned cir- cuit, primarily due to the high-side mosfet switching losses. pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention (figure 13). refer to the MAX1816/max1994 ev kit data sheet for a specific layout example. if possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. follow these guidelines for good pc board layout: 1) isolate the power components on the top side from the sensitive analog components on the bottom side with a ground shield. use a separate pgnd plane under the buck1 and buck2 sides (called pgnd1 and pgnd2). avoid the introduction of ac currents into the pgnd1 and pgnd2 ground planes. 2) use a star ground connection on the power plane to minimize the crosstalk between buck1 and buck2. 3) keep the high-current paths short, especially at the ground terminals. this is essential for stable, jitter- free operation. 4) connect all analog grounds to a separate solid copper plane, which connects to the agnd pin of the MAX1816/max1994. this includes the v cc bypass capacitor, ref bypass capacitor, compen- sation components, the time resistor, as well as any other resistive dividers. 5) tie agnd and pgnd together close to the ic. do not connect them together anywhere else. carefully follow the grounding instructions in the layout procedure . 6) in high-current master-slave applications, the mas- ter controller should have a separate analog ground. return the appropriate noise-sensitive components to this plane. since the reference in the master is sometimes connected to the slave, it may be necessary to couple the analog ground in the master to the analog ground in the slave to pre- vent ground offsets. a low value ( 10 ? ) resistor is sufficient to link the two grounds. 7) keep the power traces and load connections short. this is essential for high efficiency. the use of thick copper pc boards (2oz vs. 1oz) can enhance full load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. 8) keep the high-current gate-driver traces (dl_, dh_, lx_, and bst_) short and wide to minimize trace resistance and inductance. this is essential for high-power mosfets that require low-impedance gate drivers to avoid shoot-through currents. 9) cs1+, cs1-, cs2, and agnd connections for cur- rent limiting must be made using kelvin-sense con- nections to guarantee the current-limit accuracy. kelvin connections to lx2 and agnd must also be made if the synchronous rectifier r ds(on) of buck2 is used for current limiting. with 8-pin so mosfets, this is best done by routing power to the mosfets from the outside using the top copper layer, while connecting gnd and lx inside (under- neath) the 8-pin so package. 10) when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. 11) route high-speed switching nodes away from sen- sitive analog areas (cc, ref, ilim_). make all pin- strap control input connections (skp_/ sdn , ilim_, etc.) to analog ground or v cc rather than power ground or v dd . dual step-down controllers plus linear- regulator controller for notebook computers 46 ______________________________________________________________________________________
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers ______________________________________________________________________________________ 47 layout procedure 1) place the power components first, with ground ter- minals adjacent (low-side mosfet sources, c in_ , c out _, d1/d2 anodes). if possible, make all these connections on the top layer with wide, copper- filled areas. 2) mount the controller ic adjacent to the low-side mos- fet, preferably on the backside in order to keep lx_, pgnd_, and the dl_ drive lines short and wide. the dl_ gate traces must be short and wide, measuring 10 to 20 squares (50 mils to 100 mils wide if the mosfet is 1in from the controller ic). 3) group the gate-drive components (bst_ diodes and capacitors, v dd bypass capacitor) together near the controller ic. 4) make the MAX1816/max1994 controllers ground connections as shown in figure 13. this diagram can be viewed as having three separate ground planes: input/output ground, where all the high- power components go; the power ground plane, where the pgnd pin and v dd bypass capacitors go; and an analog ground plane where sensitive analog components go. the analog ground plane and power ground plane must meet only at a single point close to the ic. these two planes are then connected to the high-power output ground with a short connection from pgnd to the source of the low-side mosfet (the middle of the star ground). this point must also be very close to the output capacitor ground terminal. 5) connect the output power planes (v core and sys- tem ground planes) directly to the output filter capacitor positive and negative terminals with multi- ple vias. place the entire dc-dc converter circuit as close to the cpu as is practical. chip information transistor count: 13,313 figure 13. power-stage pc board layout example power ground power ground input (v+) bottom layer top layer l1 l2 c out1 c out1 c out1 c out1 c out2 c out2 c in c in c in c in c in c in v out2 v out1 power ground via to power ground analog ground MAX1816 max1994 lx1 lx2 lx1 lx2 v dd cap v cc cap ref cap
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers 48 ______________________________________________________________________________________ 32, 44, 48l qfn .eps proprietary information approval title: document control no. 21-0144 package outline 32, 44, 48l qfn thin, 7x7x0.8 mm 1 a rev. 2 e l e l a1 a a2 e/2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
MAX1816/max1994 dual step-down controllers plus linear- regulator controller for notebook computers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 49 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. proprietary information document control no. approval title: a rev. 2 2 exposed pad variations 21-0144 package outline 32, 44, 48l qfn thin, 7x7x0.8 mm common dimensions ** note: t4877-1 is a custom 48l pkg. with 4 leads depopulated. total number of leads are 44. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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